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[PATCH] aarch64 sim vector mul bug fix
- From: Jim Wilson <jim dot wilson at linaro dot org>
- To: gdb-patches at sourceware dot org
- Cc: Nick Clifton <nickc at redhat dot com>
- Date: Sat, 24 Dec 2016 14:24:15 -0800
- Subject: [PATCH] aarch64 sim vector mul bug fix
- Authentication-results: sourceware.org; auth=none
The vector mul instruction is doing a widening multiply, but isn't
supposed to. mull does a widening multiply, mul does a regular
multiply.
The testcase works with the patch, and fails without the patch. GCC C
testsuite failures drop from 2538 to 2473.
Jim
2016-12-23 Jim Wilson <jim.wilson@linaro.org>
sim/aarch64/
* simulator.c (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make
second and fourth args same size as third arg.
sim/testsuite/sim/aarch64/
* mul.s: New.
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index be3d6c7..9da12d3 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -3724,15 +3724,15 @@ do_vec_mul (sim_cpu *cpu)
switch (INSTR (23, 22))
{
case 0:
- DO_VEC_WIDENING_MUL (full ? 16 : 8, uint16_t, u8, u16);
+ DO_VEC_WIDENING_MUL (full ? 16 : 8, uint8_t, u8, u8);
return;
case 1:
- DO_VEC_WIDENING_MUL (full ? 8 : 4, uint32_t, u16, u32);
+ DO_VEC_WIDENING_MUL (full ? 8 : 4, uint16_t, u16, u16);
return;
case 2:
- DO_VEC_WIDENING_MUL (full ? 4 : 2, uint64_t, u32, u64);
+ DO_VEC_WIDENING_MUL (full ? 4 : 2, uint32_t, u32, u32);
return;
case 3:
diff --git a/sim/testsuite/sim/aarch64/mul.s b/sim/testsuite/sim/aarch64/mul.s
new file mode 100644
index 0000000..783dba7
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/mul.s
@@ -0,0 +1,99 @@
+# mach: aarch64
+
+# Check the non-widening multiply vector instruction: mul.
+
+.include "testutils.inc"
+
+ .data
+ .align 4
+input:
+ .word 0x04030201
+ .word 0x08070605
+ .word 0x0c0b0a09
+ .word 0x100f0e0d
+m8b:
+ .word 0x10090401
+ .word 0x40312419
+m16b:
+ .word 0x10090401
+ .word 0x40312419
+ .word 0x90796451
+ .word 0x00e1c4a9
+m4h:
+ .word 0x18090401
+ .word 0x70313c19
+m8h:
+ .word 0x18090401
+ .word 0x70313c19
+ .word 0x0879b451
+ .word 0xe0e16ca9
+m2s:
+ .word 0x140a0401
+ .word 0xa46a3c19
+m4s:
+ .word 0x140a0401
+ .word 0xa46a3c19
+ .word 0xb52ab451
+ .word 0x464b6ca9
+
+ start
+ adrp x0, input
+ ldr q0, [x0, #:lo12:input]
+
+ mul v1.8b, v0.8b, v0.8b
+ mov x1, v1.d[0]
+ adrp x3, m8b
+ ldr x4, [x0, #:lo12:m8b]
+ cmp x1, x4
+ bne .Lfailure
+
+ mul v1.16b, v0.16b, v0.16b
+ mov x1, v1.d[0]
+ mov x2, v1.d[1]
+ adrp x3, m16b
+ ldr x4, [x0, #:lo12:m16b]
+ cmp x1, x4
+ bne .Lfailure
+ ldr x5, [x0, #:lo12:m16b+8]
+ cmp x2, x5
+ bne .Lfailure
+
+ mul v1.4h, v0.4h, v0.4h
+ mov x1, v1.d[0]
+ adrp x3, m4h
+ ldr x4, [x0, #:lo12:m4h]
+ cmp x1, x4
+ bne .Lfailure
+
+ mul v1.8h, v0.8h, v0.8h
+ mov x1, v1.d[0]
+ mov x2, v1.d[1]
+ adrp x3, m8h
+ ldr x4, [x0, #:lo12:m8h]
+ cmp x1, x4
+ bne .Lfailure
+ ldr x5, [x0, #:lo12:m8h+8]
+ cmp x2, x5
+ bne .Lfailure
+
+ mul v1.2s, v0.2s, v0.2s
+ mov x1, v1.d[0]
+ adrp x3, m2s
+ ldr x4, [x0, #:lo12:m2s]
+ cmp x1, x4
+ bne .Lfailure
+
+ mul v1.4s, v0.4s, v0.4s
+ mov x1, v1.d[0]
+ mov x2, v1.d[1]
+ adrp x3, m4s
+ ldr x4, [x0, #:lo12:m4s]
+ cmp x1, x4
+ bne .Lfailure
+ ldr x5, [x0, #:lo12:m4s+8]
+ cmp x2, x5
+ bne .Lfailure
+
+ pass
+.Lfailure:
+ fail