Re: [PATCH] fix for aarch64 sim tbnz bug

[Jim Wilson <jim dot wilson at linaro dot org>]

On Fri, Dec 2, 2016 at 1:31 AM, Mike Frysinger <vapier@gentoo.org> wrote:
> can we please start getting tests added to sim too ?  using gcc
> indirectly to validate the sim is a bit un

The GCC testsuite is the part that I care most about, but it does make
sense for me to be adding simulator tests.  There are currently no
interesting aarch64 tests, so it isn't clear if there is any
particular style I should be using.  So I just chose a style that
seemed OK to me.  I have tests for the last two simulator patches I
contributed.  I verified that the tests work with current sources and
fail without my two patches.

I had to make a few fixes to the existing testsuite.inc file.  I moved
.Lpass and .Lfail out of the pass and fail macros, as otherwise I end
up with duplicate definitions.  I also changed fail to return
non-zero, because it should.  I find it confusing to manually run a
testcase and see it print fail, and then return a zero exit code.

Jim

PS set_flags_for_add64 is broken, which causes adds and cmn to fail.
I have a fix, and this will be my next aarch64 sim patch, but I
haven't written a testcase yet.

2016-12-04  Jim Wilson  <jim.wilson@linaro.org>

	sim/testsuite/sim/aarch64
	* testutils.inc (pass): Move .Lpass outside macro.
	(fail): Move .Lfail outside macro.  Return 1 instead of 0.
	* fstur.s: New.
	* tbnz.s: New.

diff --git a/sim/testsuite/sim/aarch64/fstur.s b/sim/testsuite/sim/aarch64/fstur.s
new file mode 100644
index 0000000..2206ae5
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/fstur.s
@@ -0,0 +1,136 @@
+# mach: aarch64
+
+# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq.
+# Check the values -1, and XXX_MAX, which tests all bits.
+# Check with offsets -256 and 255, which tests all bits.
+# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq.
+
+.include "testutils.inc"
+
+	.data
+fm1:
+	.word 3212836864
+fmax:
+	.word 2139095039
+ftmp:
+	.word 0
+
+dm1:
+	.word 0
+	.word -1074790400
+dmax:
+	.word 4294967295
+	.word 2146435071
+dtmp:
+	.word 0
+	.word 0
+
+ldm1:
+	.word	0
+	.word	0
+	.word	0
+	.word	-1073807360
+ldmax:
+	.word	4294967295
+	.word	4294967295
+	.word	4294967295
+	.word	2147418111
+ldtmp:
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+
+	start
+	adrp x1, ftmp
+	add x1, x1, :lo12:ftmp
+
+	adrp x0, fm1
+	add x0, x0, :lo12:fm1
+	sub x5, x0, #255
+	sub x6, x1, #255
+	movi d2, #0
+	ldur s2, [x5, #255]
+	stur s2, [x6, #255]
+	ldr w3, [x0]
+	ldr w4, [x1]
+	cmp w3, w4
+	bne .Lfailure
+
+	adrp x0, fmax
+	add x0, x0, :lo12:fmax
+	add x5, x0, #256
+	add x6, x1, #256
+	movi d2, #0
+	ldur s2, [x5, #-256]
+	stur s2, [x6, #-256]
+	ldr w3, [x0]
+	ldr w4, [x1]
+	cmp w3, w4
+	bne .Lfailure
+
+	adrp x1, dtmp
+	add x1, x1, :lo12:dtmp
+
+	adrp x0, dm1
+	add x0, x0, :lo12:dm1
+	sub x5, x0, #255
+	sub x6, x1, #255
+	movi d2, #0
+	ldur d2, [x5, #255]
+	stur d2, [x6, #255]
+	ldr x3, [x0]
+	ldr x4, [x1]
+	cmp x3, x4
+	bne .Lfailure
+
+	adrp x0, dmax
+	add x0, x0, :lo12:dmax
+	add x5, x0, #256
+	add x6, x1, #256
+	movi d2, #0
+	ldur d2, [x5, #-256]
+	stur d2, [x6, #-256]
+	ldr x3, [x0]
+	ldr x4, [x1]
+	cmp x3, x4
+	bne .Lfailure
+
+	adrp x1, ldtmp
+	add x1, x1, :lo12:ldtmp
+
+	adrp x0, ldm1
+	add x0, x0, :lo12:ldm1
+	sub x5, x0, #255
+	sub x6, x1, #255
+	movi v2.2d, #0
+	ldur q2, [x5, #255]
+	stur q2, [x6, #255]
+	ldr x3, [x0]
+	ldr x4, [x1]
+	cmp x3, x4
+	bne .Lfailure
+	ldr x3, [x0, 8]
+	ldr x4, [x1, 8]
+	cmp x3, x4
+	bne .Lfailure
+
+	adrp x0, ldmax
+	add x0, x0, :lo12:ldmax
+	add x5, x0, #256
+	add x6, x1, #256
+	movi v2.2d, #0
+	ldur q2, [x5, #-256]
+	stur q2, [x6, #-256]
+	ldr x3, [x0]
+	ldr x4, [x1]
+	cmp x3, x4
+	bne .Lfailure
+	ldr x3, [x0, 8]
+	ldr x4, [x1, 8]
+	cmp x3, x4
+	bne .Lfailure
+
+	pass
+.Lfailure:
+	fail
diff --git a/sim/testsuite/sim/aarch64/tbnz.s b/sim/testsuite/sim/aarch64/tbnz.s
new file mode 100644
index 0000000..2416101
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/tbnz.s
@@ -0,0 +1,55 @@
+# mach: aarch64
+
+# Check the test-bit-and-branch instructions: tbnz, and tbz.
+# We check the edge condition bit positions: 0, 1<<31, 1<<32, 1<<63.
+
+.include "testutils.inc"
+
+	start
+	mov x0, #1
+	tbnz x0, #0, .L1
+	fail
+.L1:
+	tbz x0, #0, .Lfailure
+	mov x0, #0xFFFFFFFFFFFFFFFE
+	tbnz x0, #0, .Lfailure
+	tbz x0, #0, .L2
+	fail
+.L2:
+
+	mov x0, #0x80000000
+	tbnz x0, #31, .L3
+	fail
+.L3:
+	tbz x0, #31, .Lfailure
+	mov x0, #0xFFFFFFFF7FFFFFFF
+	tbnz x0, #31, .Lfailure
+	tbz x0, #31, .L4
+	fail
+.L4:
+
+	mov x0, #0x100000000
+	tbnz x0, #32, .L5
+	fail
+.L5:
+	tbz x0, #32, .Lfailure
+	mov x0, #0xFFFFFFFEFFFFFFFF
+	tbnz x0, #32, .Lfailure
+	tbz x0, #32, .L6
+	fail
+.L6:
+
+	mov x0, #0x8000000000000000
+	tbnz x0, #63, .L7
+	fail
+.L7:
+	tbz x0, #63, .Lfailure
+	mov x0, #0x7FFFFFFFFFFFFFFF
+	tbnz x0, #63, .Lfailure
+	tbz x0, #63, .L8
+	fail
+.L8:
+
+	pass
+.Lfailure:
+	fail
diff --git a/sim/testsuite/sim/aarch64/testutils.inc b/sim/testsuite/sim/aarch64/testutils.inc
index c8897aa..99057af 100644
--- a/sim/testsuite/sim/aarch64/testutils.inc
+++ b/sim/testsuite/sim/aarch64/testutils.inc
@@ -43,11 +43,11 @@
 	
 	swiwrite 5
 	exit 0
+	.endm
 
 	.data
 .Lpass:
 	.asciz "pass\n"
-	.endm
 
 # MACRO: fail
 # Write 'fail' to stdout and quit
@@ -56,12 +56,12 @@
 	adrp	x1, .Lfail
 	add	x1, x1, :lo12:.Lfail
 	swiwrite 5
-	exit 0
+	exit 1
+	.endm
 
 	.data
 .Lfail:
 	.asciz "fail\n"
-	.endm
 
 # MACRO: start
 # All assembler tests should start with a call to "start"