[PATCH 10/17] Fix spelling in comments in .cpu files (cpu)

[Ambrogino Modigliani <ambrogino dot modigliani at gmail dot com>]

cpu/ChangeLog:

	* m32c.cpu: Fix spelling in comments.
	* m32r.cpu: Fix spelling in comments.
	* mt.cpu: Fix spelling in comments.
	* or1k.cpu: Fix spelling in comments.
	* xstormy16.cpu: Fix spelling in comments.
---
 cpu/m32c.cpu      | 2 +-
 cpu/m32r.cpu      | 2 +-
 cpu/mt.cpu        | 2 +-
 cpu/or1k.cpu      | 2 +-
 cpu/xstormy16.cpu | 8 ++++----
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu
index bcc3616..7d313bc 100644
--- a/cpu/m32c.cpu
+++ b/cpu/m32c.cpu
@@ -10292,7 +10292,7 @@
 (binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem)
 
 ;-------------------------------------------------------------
-; stzx - store on zero extention
+; stzx - store on zero extension
 ;-------------------------------------------------------------
 
 (define-pmacro (stzx-sem mode src1 src2 dst)
diff --git a/cpu/m32r.cpu b/cpu/m32r.cpu
index 003c848..8de8a43 100644
--- a/cpu/m32r.cpu
+++ b/cpu/m32r.cpu
@@ -742,7 +742,7 @@
 (dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
 (dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
 
-; These hardware elements are refered to frequently.
+; These hardware elements are referred to frequently.
 
 (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
 (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
diff --git a/cpu/mt.cpu b/cpu/mt.cpu
index bb987f3..bf49a28 100644
--- a/cpu/mt.cpu
+++ b/cpu/mt.cpu
@@ -163,7 +163,7 @@
 ; f-imm16: 16 bit immediate value when not an offset.
 ; f-imm16a: 16 bit immediate value when it's a pc-rel offset.
 ; f-uu4a: unused 4 bit field.
-; f-uu4b: second unsed 4 bit field.
+; f-uu4b: second unused 4 bit field.
 ; f-uu1: unused 1 bit field
 ; f-uu12: unused 12 bit field.
 ; f-uu16: unused 16 bit field.
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index 3a932bc..169344c 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -20,7 +20,7 @@
 (include "simplify.inc")
 
 ; The OpenRISC family is a set of RISC microprocessor architectures with an
-; emphasis on scalability and is targetted at embedded use.
+; emphasis on scalability and is targeted at embedded use.
 ; The CPU RTL development is a collaborative open source effort.
 ; http://opencores.org/or1k
 ; http://openrisc.net
diff --git a/cpu/xstormy16.cpu b/cpu/xstormy16.cpu
index ae7e042..61b27cb 100644
--- a/cpu/xstormy16.cpu
+++ b/cpu/xstormy16.cpu
@@ -941,7 +941,7 @@
 		   (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2))
 	       (set Rs (add Rs (add ws2 1)))
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; addition *is* propogated into the base register.
+	       ; addition *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (add Rb 1)))
 	       )
      ()
@@ -954,7 +954,7 @@
      (+ OP1_6 OP2A_C ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
      (sequence ()
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; subtraction *is* propogated into the base register.
+	       ; subtraction *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (sub Rb 1)))
 	       (set Rs (sub Rs (add ws2 1)))
 	       (if ws2
@@ -990,7 +990,7 @@
 	       (set-psw-nowrite (index-of Rdm) Rdm ws2)
 	       (set Rs (add Rs (add ws2 1)))
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; addition *is* propogated into the base register.
+	       ; addition *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (add Rb 1)))
 	       )
      ()
@@ -1003,7 +1003,7 @@
      (+ OP1_6 OP2A_E ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
      (sequence ()
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; subtraction *is* propogated into the base register.
+	       ; subtraction *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (sub Rb 1)))
 	       (set Rs (sub Rs (add ws2 1)))
 	       (set-psw-nowrite (index-of Rdm) Rdm ws2)
-- 
2.7.4