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Re: [PATCH 02/24] Add MIPS32 FPU64 GDB target descriptions
- From: "Maciej W. Rozycki" <macro at imgtec dot com>
- To: James Hogan <james dot hogan at imgtec dot com>
- Cc: Bhushan Attarde <bhushan dot attarde at imgtec dot com>, <gdb-patches at sourceware dot org>, Matthew Fortune <Matthew dot Fortune at imgtec dot com>, Andrew Bennett <Andrew dot Bennett at imgtec dot com>, Jaydeep Patil <Jaydeep dot Patil at imgtec dot com>, <linux-mips at linux-mips dot org>
- Date: Wed, 12 Oct 2016 17:29:53 +0100
- Subject: Re: [PATCH 02/24] Add MIPS32 FPU64 GDB target descriptions
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Thanks for your input!
Cc-ing linux-mips for the discussion about a ptrace(2) kernel API update;
anyone interested in previous talk about this change please have a look
at: <https://sourceware.org/ml/gdb-patches/2016-06/msg00441.html> and
<https://sourceware.org/ml/gdb-patches/2016-10/msg00311.html> for the
> > Hmm, has Linux kernel support for CP0.Config5 accesses gone upstream
> > already? Can you give me an upstream commit ID and/or reference to the
> > discussion where it has been approved if so?
> I don't think it did go upstream yet.
> > More importantly, what do we need CP0.Config5 access for in the first
> > place? It looks to me like this bit is irrelevant to GDB as it does not
> > affect the native (raw) register format. So the only use would be to let
> > the user running a debugging session switch between the FRE and NFRE modes
> > without the need to poke at CP1C.FRE or CP1C.NFRE registers with a CTC1
> > instruction, which by itself makes sense to me, but needs a further
> > consideration.
> It allows the FRE bit to be read (I seem to remember this was the only
> bit actually exposed through ptrace by the patch).
Then I think it makes sense even more not to create this artificial API
and use the CP1C.FRE/CP1C.NFRE registers instead which do correspond to
what hardware presents to user software. Also with CP1C.UFR/CP1C.UNFR vs
CP0.Status; while we want to retain the latter register in the view for
historical reasons, it has always been read-only and I think it ought to
remain such, with any writes to CP0.Status.FR executed via the former CP1C
> FRE simply causes certain instructions (all single precision FP
> arithmetic instructions and FP word loads/stores) to trap to the kernel
> so that it can emulate a variation/subset of FR=0, so the debugger would
> use it to decide how to decode the single precision FP registers based
> on the double precision FP registers (iirc).
I don't think there is any value in it for GDB, I think all 64-bit FP
registers ought to remain being presented as doubles and pairs of singles
regardless of the mode selected (and also possibly fixed-point longs and
pairs of fixed-point words). We don't know what's emulated and what's not
after all, and then the contents of FPRs are not interpreted by GDB itself
anyhow except in user-supplied expressions or assignment requests, which
for users' convenience I think should retain the maximum flexibility
So as I say it looks to me like the only, though obviously valid and
wholeheartedly supported, use for CP1C.FRE/CP1C.NFRE would be for user's
control of the execution environment.
> > Additionally exposing CP0.Config5 may have security implications,
> > especially as parts of the register have not been defined yet in the
> > architectures and we'd have to force architecture maintainers somehow to
> > ask us every time they intend to add a bit to this register to check if
> > this has security implications and has to be avoided and/or explicitly
> > handled in software.
> yes, as above it explicity only shows certain bits. I'm fine with the
> api changing if necessary though since it isn't upstream.
It sounds like a plan to me then -- any further questions or comments
about the kernel API part, anyone?