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[PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue
- From: Yao Qi <qiyaoltc at gmail dot com>
- To: gdb-patches at sourceware dot org
- Date: Fri, 19 Aug 2016 14:34:36 +0100
- Subject: [PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue
- Authentication-results: sourceware.org; auth=none
Nowadays, we only match pre-indexed STP in prologue. Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle. That is to say, previously GCC generates prologue like this,
sub sp, sp, #490
stp x29, x30, [sp, #-96]!
mov x29, sp
with the gcc patch above, GCC generates prologue like like this,
sub sp, sp, #4f0
stp x29, x30, [sp]
mov x29, sp
This patch is to teach GDB to recognize this instruction in prologue
analysis. It fixes some fails in gdb.base/break-interp.exp.
Regression tested on aarch64-linux with GCC mainline and 4.9.3.
I'll push it in.
gdb:
2016-08-19 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
based STP instruction.
---
gdb/aarch64-tdep.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index e97e2f4..3b7e954 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -322,10 +322,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
is64 ? 8 : 4, regs[rt]);
}
else if ((inst.opcode->iclass == ldstpair_off
- || inst.opcode->iclass == ldstpair_indexed)
- && inst.operands[2].addr.preind
+ || (inst.opcode->iclass == ldstpair_indexed
+ && inst.operands[2].addr.preind))
&& strcmp ("stp", inst.opcode->name) == 0)
{
+ /* STP with addressing mode Pre-indexed and Base register. */
unsigned rt1 = inst.operands[0].reg.regno;
unsigned rt2 = inst.operands[1].reg.regno;
unsigned rn = inst.operands[2].addr.base_regno;
--
1.9.1