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Re: [PATCH V2 0/2] Split tdesc_(amd64|i386)_mpx into tdesc(amd64|i386)_mpx_* and tdesc(amd64|i386)_avx_mpx_*
- From: Yao Qi <qiyaoltc at gmail dot com>
- To: Walfred Tedeschi <walfred dot tedeschi at intel dot com>
- Cc: palves at redhat dot com, brobecker at adacore dot com, gdb-patches at sourceware dot org
- Date: Thu, 14 Apr 2016 11:29:13 +0100
- Subject: Re: [PATCH V2 0/2] Split tdesc_(amd64|i386)_mpx into tdesc(amd64|i386)_mpx_* and tdesc(amd64|i386)_avx_mpx_*
- Authentication-results: sourceware.org; auth=none
- References: <1457025942-23711-1-git-send-email-walfred dot tedeschi at intel dot com>
Walfred Tedeschi <firstname.lastname@example.org> writes:
> CPU features can occur in any combination. The current assumption that
> feature "A" implies in feature "B" does not necessarily hold.
> This patch series construct an additional combination of the Intel(R)
> Memory Protection Extensions (MPX) with Intel(R) Advanced Vector
> Extensions (AVX).
First of all, I am not against your patches. Just think a little more
after reading them...
This reveals a problem in gdb target description. It doesn't scale very
well if processors have multiple different features, and features can be
combined differently. A processor family has three features A, B, and
C, and each processor implementation may have one, two or three of these
features. In gdb target description, we need to have many *.xml and *.c
files, for these combinations like, A, B, C, AB, AC, BC, and ABC.
The root cause is that target description are static and pre-generated.
If the target description can be generated dynamically according to the
cpuid or AT_HWCAP, that would be simpler. In this way, we only have to
define target descriptions for feature A, B, and C, and GDB/GDBserver
combine them together in the runtime.