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Re: [PATCH 4/8] Implement target_emit_ops
- From: Yao Qi <qiyaoltc at gmail dot com>
- To: Antoine Tremblay <antoine dot tremblay at ericsson dot com>
- Cc: Yao Qi <qiyaoltc at gmail dot com>, <gdb-patches at sourceware dot org>, Pierre Langlois <pierre dot langlois at arm dot com>
- Date: Mon, 08 Feb 2016 17:30:19 +0000
- Subject: Re: [PATCH 4/8] Implement target_emit_ops
- Authentication-results: sourceware.org; auth=none
- References: <1442230282-20751-1-git-send-email-pierre dot langlois at arm dot com> <1442580184-22562-1-git-send-email-yao dot qi at linaro dot org> <1442580184-22562-5-git-send-email-yao dot qi at linaro dot org> <56B50172 dot 7040608 at ericsson dot com>
Antoine Tremblay <antoine.tremblay@ericsson.com> writes:
> I'm wondering is there a reason we don't use gcc to generate the
> native bytecode like done on x86 ?
>
> x86 has a macro like so :
>
> #define EMIT_ASM(NAME, INSNS)
> do
> {
> extern unsigned char start_ ## NAME, end_ ## NAME;
> add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME);
> __asm__ ("jmp end_" #NAME "\n"
> "\t" "start_" #NAME ":"
> "\t" INSNS "\n"
> "\t" "end_" #NAME ":");
> } while (0)
>
The reason is about the code readability. We find the way we are using
in aarch64 is more readable than the way for x86.
p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
p += emit_add (p, fp, sp, immediate_operand (2 * 8));
vs.
EMIT_ASM (amd64_prologue,
"pushq %rbp\n\t"
"movq %rsp,%rbp\n\t"
"sub $0x20,%rsp\n\t"
"movq %rdi,-8(%rbp)\n\t"
"movq %rsi,-16(%rbp)");
> Could the same be done for armv7 or there's a reason that prevents it ?
>
No reason prevents it, but the code should be readable.
--
Yao (éå)