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Re: [PATCH] aarch64 multi-arch part 6: HW breakpoint on unaligned address
- From: Pedro Alves <palves at redhat dot com>
- To: Yao Qi <qiyaoltc at gmail dot com>
- Cc: gdb-patches at sourceware dot org
- Date: Thu, 15 Oct 2015 14:02:46 +0100
- Subject: Re: [PATCH] aarch64 multi-arch part 6: HW breakpoint on unaligned address
- Authentication-results: sourceware.org; auth=none
- References: <1444731060-16237-1-git-send-email-yao dot qi at linaro dot org> <561CE5D2 dot 8030505 at redhat dot com> <861tcy6b84 dot fsf at gmail dot com> <561D4008 dot 90009 at redhat dot com> <86fv1c4kg7 dot fsf at gmail dot com>
On 10/15/2015 09:14 AM, Yao Qi wrote:
> Pedro Alves <email@example.com> writes:
>> At least the comment should be updated. It's quite misleading as is.
> In order to do 32-bit check in nat/aarch64-linux-hw-point.c, I add a new
> regcache interface regcache_register_size which is defined in both GDB
> and GDBserver. It has two arguments, regcache and number, which looks
> more reasonable than register_size, IMO. With regcache_register_size in
> place, we can check 32-bit like this,
> struct regcache *regcache
> = get_thread_regcache_for_ptid (current_lwp_ptid ());
> /* Set alignment to 2 only if the current process is 32-bit,
> since thumb instruction can be 2-byte aligned. Otherwise, set
> alignment to AARCH64_HBP_ALIGNMENT. */
> if (regcache_register_size (regcache, 0) == 8)
> alignment = AARCH64_HBP_ALIGNMENT;
> alignment = 2;
> on the other hand, a lot of register_size calls in GDB and GDBserver can
> be replaced by regcache_register_size. This can be done separately.
> Here is the patch V2, regression tested on aarch64-linux.