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[PATCH] Detect 64-bit-ness in PowerPC Book III-E

This patch is to teach GDBServer to detect 64-bit inferior correctly.
We find a problem that GDBServer is unable to detect on an e5500 core
processor.  Current GDBServer assumes that MSR is a 64-bit register,
but MSR is a 32-bit register in Book III-E.  This patch is to fix this
problem by checking both bits in MSR, in order to handle both Book
III-S and Book III-E.

Is it OK?


2014-12-11  Yao Qi  <>

	* linux-ppc-low.c (ppc_arch_setup) [__powerpc64__]: Change
	variable msr to type 'unsigned long'.  Check bit 63 or bit 31
	is one.
 gdb/gdbserver/linux-ppc-low.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
index 8fd4b38..0c0ced6 100644
--- a/gdb/gdbserver/linux-ppc-low.c
+++ b/gdb/gdbserver/linux-ppc-low.c
@@ -401,7 +401,7 @@ ppc_arch_setup (void)
   const struct target_desc *tdesc;
 #ifdef __powerpc64__
-  long msr;
+  unsigned long msr;
   struct regcache *regcache;
   /* On a 64-bit host, assume 64-bit inferior process with no
@@ -411,13 +411,17 @@ ppc_arch_setup (void)
   current_process ()->tdesc = tdesc;
   ppc_hwcap = 0;
-  /* Only if the high bit of the MSR is set, we actually have
-     a 64-bit inferior.  */
+  /* We actually have a 64-bit inferior only if the certain bit of the
+     MSR is set.  The PowerISA Book III-S MSR is different from the
+     PowerISA Book III-E MSR.  The Book III-S MSR is 64 bits wide, and
+     its MSR[SF] is the bit 0 of a 64-bit value.  Book III-E MSR is 32
+     bits wide, and its MSR[CM] is the bit 0 of a 32-bit value.  We check
+     both here.  */
   regcache = new_register_cache (tdesc);
   fetch_inferior_registers (regcache, find_regno (tdesc, "msr"));
   collect_register_by_name (regcache, "msr", &msr);
   free_register_cache (regcache);
-  if (msr < 0)
+  if (msr & 0x8000000080000000)
       ppc_get_hwcap (&ppc_hwcap);
       if (ppc_hwcap & PPC_FEATURE_CELL)

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