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Re: [RFC][PATCH] arm-tdep.c (arm_m_exception_cache): Handle stack switching to PSP during exception unwind.

On 09/23/2014 01:22 PM, Yao Qi wrote:
> Pedro Alves <> writes:
>> Let's start by fixing this properly, please.  If GDB needs to know
>> about these registers, then they should be part of a known feature
>> in the target description.  According to B1.4 in the same document,
>> we see:
>> "The ARMv7-M profile has the following registers closely coupled to the core:
>> - general purpose registers R0-R12
>> - 2 Stack Pointer registers, SP_main and SP_process (banked versions of R13)
>> - the Link Register, LR (R14)
>> - the Program Counter, PC
>> - status registers for flags, exception/interrupt level, and execution state bits
>> - mask registers associated with managing the prioritization scheme
>> for exceptions and interrupts
>> - a control register (CONTROL) to identify the current stack and
>> thread mode privilege level.
>> "
>> Seems like even more core things other than SP_main/SP_process are
>> missing from org.gnu.gdb.arm.m-profile, when debugging at this level.
> If we add more registers to feature org.gnu.gdb.arm.m-profile, xml files
> provided by gdb stubs (such as openocd) have to be updated too,
> otherwise GDB will reject the target description, right?  Does this
> cause any compatibility issue? new gdb rejects the target description
> from old openocd.

Right, just making GDB expect more registers in the existing feature
would be a problem for compatibility.  So we don't add new registers to
existing features.  Instead we either:

 - create a replacement feature for "org.gnu.gdb.arm.m-profile" with
   the full set of core registers.
 - or create a separate feature for the missing registers, and have
   the reported target description include both
   the "org.gnu.gdb.arm.m-profile" feature and the new feature.

I'm guessing org.gnu.gdb.arm.m-profile doesn't include those
exception/interrupt related registers as these aren't available to
userspace programs (*) ?  Do non-M-profile ARMs have them too?

(*) BTW, if so, what does ARM call the mode that allows access
to these registers?  "kernel mode", or something else?

Pedro Alves

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