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[PATCH] Power: Correct little-endian e500v2 GPR frame offsets


Hi,

 This change corrects GPR frame offset calculation for the e500v2 
processor.  On this target, featuring the SPE APU, GPRs are 64-bit and are 
held in stack frames whole with the use of `evstdd' and `evldd' 
instructions.  Their integer 32-bit part occupies the low-order word and 
therefore its offset varies between the two endiannesses possible.  Code 
in rs6000_frame_cache however assumes the big endianness and 
unconditionally uses an offset of 4 from the address of the whole 64-bit 
quantity in memory.  This causes a failure in little-endian testing:

(gdb) PASS: gdb.base/return-nodebug.exp: double: return from function with no debug info without a cast
return (double) -1
Make selected stack frame return now? (y or n) y
#0  0x100002dc in main () at .../gdb/testsuite/gdb.base/return-nodebug.c:30
30        t = func ();
(gdb) PASS: gdb.base/return-nodebug.exp: double: return from function with 
no debug info with a cast
advance marker
marker () at .../gdb/testsuite/gdb.base/return-nodebug.c:23
23      }
(gdb) PASS: gdb.base/return-nodebug.exp: double: advance to marker
print /d t
$1 = 0
(gdb) FAIL: gdb.base/return-nodebug.exp: double: full width of the returned result

The change below addresses the problem by assuming an offset of 0 for 
little-endian targets.

 Regression-tested for both endiannesses with the powerpc-eabi target 
(`-mcpu=8548 -mfloat-gprs=double -mspe=yes -mabi=spe' GCC options) and no 
changes in results other than fixing the little-endian failure described 
above.

 OK to apply?

2014-02-28  Maciej W. Rozycki  <macro@codesourcery.com>

	gdb/
	* rs6000-tdep.c (rs6000_frame_cache): Correct little-endian
	GPR offset into SPE pseudo registers.

  Maciej

gdb-rs6000-ev-gpr-le.diff
Index: gdb-fsf-trunk-quilt/gdb/rs6000-tdep.c
===================================================================
--- gdb-fsf-trunk-quilt.orig/gdb/rs6000-tdep.c	2014-02-28 23:14:50.298928402 +0000
+++ gdb-fsf-trunk-quilt/gdb/rs6000-tdep.c	2014-02-28 23:15:04.298928235 +0000
@@ -3257,12 +3257,13 @@ rs6000_frame_cache (struct frame_info *t
 	{
 	  int i;
 	  CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
+	  CORE_ADDR off = byte_order == BFD_ENDIAN_BIG ? 4 : 0;
 	  for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
 	    {
 	      cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
-              cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
+	      cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off;
 	      ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
-            }
+	    }
 	}
     }
 


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