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[PATCH 1/1] Documentation for MPX.

From: Walfred Tedeschi <>

Hello Eli and Pedro,

This should complement the MPX registers check-in.

Thanks a lot for your review on the last patch series.
Here I have tried to incorporate feedback from you both.


2013-1X-XX  Walfred Tedeschi  <>

	* NEWS:  Add section for Intel(R) Architecture Instructions
	Extesions mentioning MPX.
	* gdb.texinfo (i386 Features): Add MPX feature registers.
	(x86 Specific featuresx86 Architecture-specific Issues): Adds
	a subsubsection for MPX and describes the display of the
	boundary registers.

 gdb/NEWS            |    2 ++
 gdb/doc/gdb.texinfo |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/gdb/NEWS b/gdb/NEWS
index 9fc3638..fdb33d4 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -5558,3 +5558,5 @@ GDB now handles cross debugging.  If you are remotely debugging between
 two different machines, type ``./configure host -target=targ''.
 Host is the machine where GDB will run; targ is the machine
 where the program that you are debugging will run.
+ *  GDB now supports access to Intel(R) MPX registers on GNU/Linux.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index d854f46..6041b4a 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -21363,6 +21363,42 @@ be returned in a register.
 @kindex show struct-convention
 Show the current setting of the convention to return @code{struct}s
 from functions.
+@subsubsection Intel(R) Memory Protection Extensions (MPX).
+@item bnd0raw..bnd3raw and bnd0...bnd3 registers display.
+Memory Protection Extension (MPX) adds the bound registers @samp{BND0}
+@footnote{Capital letters are used to distinguish between architecture
+registers and pseudo registers.  A set of pseudo registers for the bound
+registers is created to simplify the display.} through @samp{BND3}.  Bound
+registers store a pair of 64-bit values which are the lower bound and upper
+bound.  Bounds are effective addresses or memory locations.  The upper bounds
+are architecturally represented in 1's complement form.  A bound having lower
+bound = 0, and upper bound = 0 (1's complement of all bits set) will allow
+access to the entire address space.
+Architectuere registers @samp{BND0} through @samp{BND3} are
+represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}.
+Pseudo registers @samp{bnd0} through @samp{bnd3} display the upper bound
+performing the complement of one operation on the upper bound value, i.e.@
+when upper bound in @samp{bnd0raw} is 0 in the @value{GDBN} @samp{bnd0} it will
+be @code{0xfff...}.  In this sense it can also be noted that the upper bounds are
+As an example, assume that the register BND0 holds bounds for a pointer having
+access allowed for the range between 0x32 and 0x71.  The values present on
+bnd0raw and bnd registers are presented as follows:
+	bnd0raw = {0x32, 0xffffffff8e}
+	bnd0 = {lbound = 0x32, ubound = 0x71} : size 64
+@end smallexample
+This way the architecture value can be accessed via bnd0raw...bnd3raw.  Any change
+on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its counterpart.  When displaying
+bnd0..bnd3 register with Python support also the size of the bounds is displayed.
 @end table
 @node Alpha
@@ -43138,6 +43174,16 @@ describe the upper 128 bits of @sc{ymm} registers:
 @samp{ymm0h} through @samp{ymm15h} for amd64
 @end itemize
+The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R)
+Memory Protection Extension (MPX).  It should describe the following registers:
+@itemize @minus
+@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64.
+@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64.
+@end itemize
 The @samp{org.gnu.gdb.i386.linux} feature is optional.  It should
 describe a single register, @samp{orig_eax}.

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