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Re: [PATCH V7 8/8] Add MPX feature description to GDB manual.


On 10/09/2013 01:00 PM, Walfred Tedeschi wrote:
> +The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R)
> +Memory Protection Extension (MPX).  MPX adds the bound registers @samp{BND0}
> +@footnote{Capital letters were used to distinguish between architecture
> +registers and pseudo registers.  

I'd suggest s/were/are.  (here and elsewhere)

> A set of pseudo register for the bound
> +registers were created to simplify the display.} through @samp{BND3}.  Bound
> +registers store a pair of 64-bit values which are the lower bound and upper
> +bound.  Bounds are effective addresses or memory locations.  The upper bounds
> +are architecturally represented in 1's complement form.  A bound having lower
> +bound = 0, and upper bound = 0 (1's complement of all bits set) will allow
> +access to the entire address space.
> +
> +In order to take the upper bound complement
> +of one into account the @samp{BND0} through @samp{BND3} are described in GDB
> +as @samp{bnd0raw} through @samp{bnd3raw}.  Pseudo registers @samp{bnd0} through
> +@samp{bnd3} display the upper bound performing the complement of one operation,
> +i.e.@ when upper bound in @samp{bnd0raw} is 0 in the GDB @samp{bnd0} it will be
> +@code{0xfff...}.  The feature adds the following registers:

This node is mostly meant for remote stub writers.
I'd suggest only describing here what's included in the description (the raw
registers), and describe the pseudo registers elsewhere where regular users will
look (making sure to word things in a user-friendly way, perhaps with examples.)

Perhaps in Architectures->i386  (x86 Architecture-specific Issues)?

> +
> +@itemize @minus
> +@item
> +@samp{bnd0raw} through @samp{bnd3raw} for i386, amd64 and x32.
> +@item
> +@samp{bndcfgu} and @samp{bndstatus} for i386, amd64 and x32.
> +@end itemize
> +
>  The @samp{org.gnu.gdb.i386.linux} feature is optional.  It should
>  describe a single register, @samp{orig_eax}.


-- 
Pedro Alves


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