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[PATCH] Add MIPS UFR support


This patch adds support to the MIPS backend to deal with changing the FR mode in user mode
(which I will now refer to as UFR).  The technical details are explained in the following paragraph.

The read only field UFR (at bit 28) in the floating point implementation register (CP1 control register 0) 
represents if the CPU supports UFR.  The UFR field (bit 2) in configuration register 5 (CP0 register 16, 
select 5) allows user mode to enable or disable UFR support.  The current value of the FR mode can be 
obtained if a read is made from the UFR register (CP1 control register 1), and UFR support is enabled.  
If register zero is written to the UFR register, and UFR support is enabled, then the FR mode is set to 0.  
If register zero is written to the UNFR register (CP1 control register 4), and the UFR support is enabled, 
then the FR mode is set to 1.  

To implement this I have firstly added the config 5 register to the simulator model, and added support to 
read and write to it.  Secondly, I have added support for the CTC1 and CFC1 instructions to write/read 
to/from the UFR and UNFR registers.

I have also added a testcase to validate the implementation.  To run the testcase you will need to apply 
the following binutils patch:

The simulator patch is attached to this email and the ChangeLog is shown below.  

This is my first patch to gdb, so I am unsure the protocol on committing.  Would someone be able to clarify?

Many thanks,


2013-11-08  Andrew Bennett  <>
	* interp.c (ColdReset): Reset the config 5 register and
	set FCR0 to allow user mode FR switching instructions.
	(decode_coproc): Add support for reading and setting the config 5
	* mips.igen (CTC1c): Add UFR support.
	(CFC1c): Likewise.
	* sim-main.h (_sim_cpu): Add config 5 register and support macros.

	* basic.exp: Added ufr testcase.
	* ufr.s: New.

Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814

Attachment: gnusim-ufr.patch
Description: gnusim-ufr.patch

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