This is the mail archive of the
gdb-patches@sourceware.org
mailing list for the GDB project.
[PATCH V5 8/8] Add MPX feature description to GDB manual.
- From: Walfred Tedeschi <walfred dot tedeschi at intel dot com>
- To: tromey at redhat dot com, gdb-patches at sourceware dot org, mark dot kettenis at xs4all dot nl
- Cc: Walfred Tedeschi <walfred dot tedeschi at intel dot com>
- Date: Mon, 9 Sep 2013 14:24:41 +0200
- Subject: [PATCH V5 8/8] Add MPX feature description to GDB manual.
- Authentication-results: sourceware.org; auth=none
- References: <1378729481-9105-1-git-send-email-walfred dot tedeschi at intel dot com>
Describes MPX feature registers including bnd0raw ... bnd3raw, bnd0 ... bnd3
bndstatus and bndcfgu. News adds the section for Intel(R) Architecture
Instructions Extensions and mention the MPX support.
2013-08-30 Walfred Tedeschi <walfred.tedeschi>
* NEWS: Add section for Intel(R) Architecture Instructions
Extesions mentioning MPX.
doc/
* gdb.texinfo (i386 Features): Add MPX feature.
---
gdb/NEWS | 2 ++
gdb/doc/gdb.texinfo | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index ca8baea..fc58cc4 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -5464,3 +5464,5 @@ GDB now handles cross debugging. If you are remotely debugging between
two different machines, type ``./configure host -target=targ''.
Host is the machine where GDB will run; targ is the machine
where the program that you are debugging will run.
+
+ * GDB now supports access to Intel(R) MPX registers on GNU/Linux.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 21250fe..353c389 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -42560,6 +42560,31 @@ describe the upper 128 bits of @sc{ymm} registers:
@samp{ymm0h} through @samp{ymm15h} for amd64
@end itemize
+The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R)
+Memory Protection Extension (MPX). MPX adds the bound registers @samp{BND0}
+@footnote{Capital letters were used to distinguish between architecture
+registers and pseudo registers. A set of pseudo register for the bound
+registers were created to simplify the display.} through @samp{BND3}. Bound
+registers store a pair of 64-bit values which are the lower bound and upper
+bound. Bounds are effective addresses or memory locations. The upper bounds
+are architecturally represented in 1's complement form. A bound having lower
+bound = 0, and upper bound = 0 (1's complement of all bits set) will allow
+access to the entire address space.
+
+In order to take the upper bound complement
+of one into account the @samp{BND0} through @samp{BND3} are described in GDB
+as @samp{bnd0raw} through @samp{bnd3raw}. Pseudo registers @samp{bnd0} through
+@samp{bnd3} display the upper bound performing the complement of one operation,
+i.e.@ when upper bound in @samp{bnd0raw} is 0 in the GDB @samp{bnd0} it will be
+@code{0xfff...}. The feature adds the following registers:
+
+@itemize @minus
+@item
+@samp{bnd0raw} through @samp{bnd3raw} for i386, amd64 and x32.
+@item
+@samp{bndcfgu} and @samp{bndstatus} for i386, amd64 and x32.
+@end itemize
+
The @samp{org.gnu.gdb.i386.linux} feature is optional. It should
describe a single register, @samp{orig_eax}.
--
1.7.10.4