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[PATCH V4 8/8] Add MPX feature description to GDB manual.
- From: Walfred Tedeschi <walfred dot tedeschi at intel dot com>
- To: tromey at redhat dot com, gdb-patches at sourceware dot org, mark dot kettenis at xs4all dot nl
- Cc: Walfred Tedeschi <walfred dot tedeschi at intel dot com>
- Date: Thu, 5 Sep 2013 11:26:28 +0200
- Subject: [PATCH V4 8/8] Add MPX feature description to GDB manual.
- Authentication-results: sourceware.org; auth=none
- References: <1378373188-31144-1-git-send-email-walfred dot tedeschi at intel dot com>
Describes MPX feature registers including bnd0raw ... bnd3raw, bnd0 ... bnd3
bndstatus and bndcfgu. News adds the section for Intel(R) Architecture
Instructions Extensions and mention the MPX support.
2013-08-30 Walfred Tedeschi <walfred.tedeschi>
* NEWS: Add section for Intel(R) Architecture Instructions
Extesions mentioning MPX.
doc/
* gdb.texinfo (i386 Features): Add MPX feature.
---
gdb/NEWS | 2 ++
gdb/doc/gdb.texinfo | 22 ++++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index ca8baea..fc58cc4 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -5464,3 +5464,5 @@ GDB now handles cross debugging. If you are remotely debugging between
two different machines, type ``./configure host -target=targ''.
Host is the machine where GDB will run; targ is the machine
where the program that you are debugging will run.
+
+ * GDB now supports access to Intel(R) MPX registers on GNU/Linux.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 21250fe..9f66992 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -42563,6 +42563,28 @@ describe the upper 128 bits of @sc{ymm} registers:
The @samp{org.gnu.gdb.i386.linux} feature is optional. It should
describe a single register, @samp{orig_eax}.
+The @samp{org.gnu.gdb.i386.mpx} feature is optional. It should
+describe the following registers:
+
+@itemize @minus
+@item
+@samp{bnd0raw} through @samp{bnd3raw} for i386, amd64 and x32. Hardware
+representation of the bound registers effectively @samp{bnd0} through
+@samp{bnd3}. The bounds are unsigned effective addresses, and are
+inclusive. The upper bounds are architecturally represented in 1's
+complement form. Lower bound = 0, and upper bound = 0
+(1's complement of all 1s) will allow access to the entire address
+space.
+@item
+@samp{bnd0} through @samp{bnd3} for i386, amd64 and x32.
+User representation of the bound registers. Upper bound value stores
+the effective address of the bound, i.e. the one's complement of the
+value stored on the upper bound of @samp{bndraw} registers.
+@item
+@samp{bndcfgu} and @samp{bndstatus} for i386, amd64 and x32.
+@end itemize
+
+
@node MIPS Features
@subsection @acronym{MIPS} Features
@cindex target descriptions, @acronym{MIPS} features
--
1.7.10.4