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Re: [PATCH] MIPS: Correct floating point condition code mask
- From: "Maciej W. Rozycki" <macro at codesourcery dot com>
- To: Joel Brobecker <brobecker at adacore dot com>
- Cc: <gdb-patches at sourceware dot org>
- Date: Wed, 7 Dec 2011 00:06:01 +0000
- Subject: Re: [PATCH] MIPS: Correct floating point condition code mask
- References: <alpine.DEB.firstname.lastname@example.org> <20111205110542.GF2777@adacore.com>
On Mon, 5 Dec 2011, Joel Brobecker wrote:
> > The floating point condition codes occupy bits 31:25 and 23 of the
> > Floating Point Control and Status Register (or have done so since the
> > R8000 and the MIPS IV ISA where codes beyond #0 were added).
> Trusting you again on this one...
The original MIPS IV ISA definition of the FCSR can be found in Appendix
B of the MIPS IV spec (007-2597-001.pdf) available from techpubs.sgi.com
(the spec consists of two appendices only; no idea where the rest is).
The current version is at mips.com ("Introduction to the MIPS32
Architecture", doc #MD00082).
> > 2011-11-23 Maciej W. Rozycki <email@example.com>
> > gdb/
> > * mips-tdep.c (mips32_next_pc): Fix floating point condition
> > code mask.
> ... Based on the above, I agree the patch makes sense. Please go ahead
> and commit.
I have committed it now, thanks for the review.