This is the mail archive of the mailing list for the GDB project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH] MIPS: Correct floating point condition code mask


 The floating point condition codes occupy bits 31:25 and 23 of the 
Floating Point Control and Status Register (or have done so since the 
R8000 and the MIPS IV ISA where codes beyond #0 were added).  The change 
below fixes the mask used by branch emulation used for figuring out the 
next instruction's address to set a breakpoint at while single-stepping; 
this affects FPU (CP1) condition branches.

 Regression tested successfully for mips-sde-elf and mips-linux-gnu.  OK 
to apply?

2011-11-23  Maciej W. Rozycki  <>

	* mips-tdep.c (mips32_next_pc): Fix floating point condition
	code mask.


Index: gdb-fsf-trunk-quilt/gdb/mips-tdep.c
--- gdb-fsf-trunk-quilt.orig/gdb/mips-tdep.c	2011-11-23 02:43:11.205560945 +0000
+++ gdb-fsf-trunk-quilt/gdb/mips-tdep.c	2011-11-23 02:43:17.315559888 +0000
@@ -1173,7 +1173,7 @@ mips32_next_pc (struct frame_info *frame
 	    get_frame_register_signed (frame,
 				       mips_regnum (get_frame_arch (frame))->
-	  int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
+	  int cond = ((fcrcs >> 24) & 0xfe) | ((fcrcs >> 23) & 0x01);
 	  if (((cond >> cnum) & 0x01) == tf)
 	    pc += mips32_relative_offset (inst) + 4;

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]