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[PATCH] RX sim btst instruction
- From: Yoshinori Sato <ysato at users dot sourceforge dot jp>
- To: gdb-patches <gdb-patches at sourceware dot org>
- Date: Tue, 22 Dec 2009 22:35:08 -0500
- Subject: [PATCH] RX sim btst instruction
"btst #imm,Rs2" and "btst Rs,Rs2" is false result.
Rs2 information is opecode.op[1].
Index: rx/ChangeLog
===================================================================
RCS file: /cvs/src/src/sim/rx/ChangeLog,v
retrieving revision 1.2
diff -u -r1.2 ChangeLog
--- rx/ChangeLog 30 Nov 2009 23:37:39 -0000 1.2
+++ rx/ChangeLog 23 Dec 2009 03:17:15 -0000
@@ -1,3 +1,7 @@
+2009-12-22 Yoshinori Sato <ysato@users.sourceforge.jp>
+
+ * rx/rx.c (decode_opcode): btst bit address mask fix.
+
2009-11-30 DJ Delorie <dj@redhat.com>
* rx/rx.c (decode_opcode): fix SWHILE logic.
Index: rx/rx.c
===================================================================
RCS file: /cvs/src/src/sim/rx/rx.c,v
retrieving revision 1.2
diff -u -r1.2 rx.c
--- rx/rx.c 30 Nov 2009 23:37:39 -0000 1.2
+++ rx/rx.c 23 Dec 2009 03:17:16 -0000
@@ -676,7 +676,7 @@
case RXO_btst:
ma = GS ();
mb = GS2 ();
- if (opcode.op[0].type == RX_Operand_Register)
+ if (opcode.op[1].type == RX_Operand_Register)
mb &= 0x1f;
else
mb &= 0x07;
--
Yoshinori Sato
<ysato@users.sourceforge.jp>