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[PATCH-ppc 5/5] Add VSX doc bits
- From: Luis Machado <luisgpm at linux dot vnet dot ibm dot com>
- To: gdb-patches at sourceware dot org
- Date: Fri, 25 Jul 2008 17:15:55 -0300
- Subject: [PATCH-ppc 5/5] Add VSX doc bits
- Reply-to: luisgpm at linux dot vnet dot ibm dot com
Last, but not the least, this adds some documentation about the new
register set. It's not very descriptive, but as the patches may change a
bit, i'll leave this one to the end. It'll probably require a NEWS entry
as well.
---
2008-07-25 Luis Machado <luisgpm@br.ibm.com>
* doc/gdb.texinfo: Updated documentation with new support info.
Index: gdb/doc/gdb.texinfo
===================================================================
--- gdb.orig/doc/gdb.texinfo 2008-07-23 09:28:06.000000000 -0700
+++ gdb/doc/gdb.texinfo 2008-07-23 09:31:44.000000000 -0700
@@ -16210,6 +16210,9 @@
by joining the even/odd register pairs @code{f0} and @code{f1} for @code{$dl0},
@code{f2} and @code{f3} for @code{$dl1} and so on.
+For POWER7 processors, GDB provides a new set of pseudo-registers, the 64-bit
+wide Extended Floating Point Registers (@samp{f32} through @samp{f63}).
+
@node Controlling GDB
@chapter Controlling @value{GDBN}
@@ -27406,6 +27409,13 @@
contain registers @samp{vr0} through @samp{vr31}, @samp{vscr},
and @samp{vrsave}.
+The @samp{org.gnu.gdb.power.vsx} feature is optional. It should
+contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN}
+will combine these registers with the floating point registers
+(@samp{f0} through @samp{f31}) and the altivec registers (@samp{vr0}
+through @samp{vr31}} to present the 128-bit wide registers @samp{vs0}
+through @samp{vs63}, the new set of vector registers for POWER7.
+
The @samp{org.gnu.gdb.power.spe} feature is optional. It should
contain registers @samp{ev0h} through @samp{ev31h}, @samp{acc}, and
@samp{spefscr}. SPE targets should provide 32-bit registers in