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[patch] Enforce register slignment for FRV
- From: Dave Brolley <brolley at redhat dot com>
- To: binutils at sources dot redhat dot com, gdb-patches at sources dot redhat dot com
- Date: Fri, 10 Oct 2003 15:35:49 -0400
- Subject: [patch] Enforce register slignment for FRV
Hi,
I've committed the attached patch which enforces register alignment on
the FRV.
Dave
2003-10-10 Dave Brolley <brolley@redhat.com>
* frv.cpu (dnpmop): New p-macro.
(GRdoublek): Use dnpmop.
(CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
(store-double-r-r): Use (.sym regtype doublek).
(r-store-double): Ditto.
(store-double-r-r-u): Ditto.
(conditional-store-double): Ditto.
(conditional-store-double-u): Ditto.
(store-double-r-simm): Ditto.
(fmovs): Assign to UNIT FMALL.
2003-10-10 Dave Brolley <brolley@redhat.com>
* frv-asm.c,frv-desc.c,frv-opc.c: Regenerated.
2003-10-10 Dave Brolley <brolley@redhat.com>
* cpu.h, sem.c: Regenerate.
2003-10-10 Dave Brolley <brolley@redhat.com>
* sim/frv/testutils.inc (or_gr_immed): New macro.
* sim/frv/fp_exception-fr550.cgs: Write insns using
unaligned registers into the program in order to
cause the required exceptions.
* sim/frv/fp_exception.cgs: Ditto.
* sim/frv/regalign.cgs: Ditto.
2003-10-10 Dave Brolley <brolley@redhat.com>
* gas/frv/allinsn.s: Use preoperly aligned registers.
* gas/frv/allinsn.d: Update expected results.
Index: cpu/frv.cpu
===================================================================
RCS file: /cvs/cvsfiles/devo/cpu/frv.cpu,v
retrieving revision 1.14
diff -c -p -r1.14 frv.cpu
*** cpu/frv.cpu 8 Oct 2003 20:26:11 -0000 1.14
--- cpu/frv.cpu 10 Oct 2003 15:25:13 -0000
***************
*** 2652,2657 ****
--- 2652,2670 ----
)
)
+ ; dnpmop: define-normal-parsed-mode-operand: Normal mode operand with parse handler
+ (define-pmacro (dnpmop xname xcomment xattrs xtype xindex xmode xparse)
+ (define-operand
+ (name xname)
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs))
+ (type xtype)
+ (index xindex)
+ (mode xmode)
+ (handlers (parse xparse))
+ )
+ )
+
(dnop pack "packing bit" () h-pack f-pack)
(dnmop GRi "source register 1" () h-gr f-GRi SI)
***************
*** 2659,2665 ****
(dnmop GRk "destination register" () h-gr f-GRk SI)
(dnmop GRkhi "destination register" () h-gr_hi f-GRk UHI)
(dnmop GRklo "destination register" () h-gr_lo f-GRk UHI)
! (dnmop GRdoublek "destination register" () h-gr_double f-GRk DI)
(dnmop ACC40Si "signed accumulator" () h-acc40S f-ACC40Si DI)
(dnmop ACC40Ui "unsigned accumulator" () h-acc40U f-ACC40Ui UDI)
(dnmop ACC40Sk "target accumulator" () h-acc40S f-ACC40Sk DI)
--- 2672,2678 ----
(dnmop GRk "destination register" () h-gr f-GRk SI)
(dnmop GRkhi "destination register" () h-gr_hi f-GRk UHI)
(dnmop GRklo "destination register" () h-gr_lo f-GRk UHI)
! (dnpmop GRdoublek "destination register" () h-gr_double f-GRk DI "even_register")
(dnmop ACC40Si "signed accumulator" () h-acc40S f-ACC40Si DI)
(dnmop ACC40Ui "unsigned accumulator" () h-acc40U f-ACC40Ui UDI)
(dnmop ACC40Sk "target accumulator" () h-acc40S f-ACC40Sk DI)
***************
*** 2670,2676 ****
(dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI)
(dnmop CPRj "source register" ((MACH frv)) h-cpr f-CPRj SI)
(dnmop CPRk "destination register" ((MACH frv)) h-cpr f-CPRk SI)
! (dnmop CPRdoublek "destination register" ((MACH frv)) h-cpr_double f-CPRk DI)
; floating point operands
(dnmop FRinti "source register 1" () h-fr_int f-FRi SI)
--- 2683,2689 ----
(dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI)
(dnmop CPRj "source register" ((MACH frv)) h-cpr f-CPRj SI)
(dnmop CPRk "destination register" ((MACH frv)) h-cpr f-CPRk SI)
! (dnpmop CPRdoublek "destination register" ((MACH frv)) h-cpr_double f-CPRk DI "even_register")
; floating point operands
(dnmop FRinti "source register 1" () h-fr_int f-FRi SI)
***************
*** 2681,2689 ****
(dnmop FRk "destination register" () h-fr f-FRk SF)
(dnmop FRkhi "destination register" () h-fr_hi f-FRk UHI)
(dnmop FRklo "destination register" () h-fr_lo f-FRk UHI)
! (dnmop FRdoublei "source register 1" () h-fr_double f-FRi DF)
! (dnmop FRdoublej "source register 2" () h-fr_double f-FRj DF)
! (dnmop FRdoublek "target register" () h-fr_double f-FRk DF)
(dnop CRi "source register 1" () h-cccr f-CRi)
(dnop CRj "source register 2" () h-cccr f-CRj)
--- 2694,2702 ----
(dnmop FRk "destination register" () h-fr f-FRk SF)
(dnmop FRkhi "destination register" () h-fr_hi f-FRk UHI)
(dnmop FRklo "destination register" () h-fr_lo f-FRk UHI)
! (dnpmop FRdoublei "source register 1" () h-fr_double f-FRi DF "even_register")
! (dnpmop FRdoublej "source register 2" () h-fr_double f-FRj DF "even_register")
! (dnpmop FRdoublek "target register" () h-fr_double f-FRk DF "even_register")
(dnop CRi "source register 1" () h-cccr f-CRi)
(dnop CRj "source register 2" () h-cccr f-CRj)
***************
*** 4498,4505 ****
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
! (.str name "$pack $" regtype "k,@($GRi,$GRj)")
! (+ pack (.sym regtype k) op GRi ope GRj)
(sequence ((WI address))
(store-double-semantics mode regtype address GRj))
profile
--- 4511,4518 ----
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
! (.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
! (+ pack (.sym regtype doublek) op GRi ope GRj)
(sequence ((WI address))
(store-double-semantics mode regtype address GRj))
profile
***************
*** 4521,4532 ****
(dni name
(comment)
((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr)
! (.str name "$pack $" regtype "k,@($GRi,$GRj)")
! (+ pack (.sym regtype k) op GRi ope GRj)
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)
(c-call VOID "@cpu@_check_recovering_store"
! address (index-of (.sym regtype k)) 8 is_float))
profile
)
)
--- 4534,4545 ----
(dni name
(comment)
((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr)
! (.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
! (+ pack (.sym regtype doublek) op GRi ope GRj)
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)
(c-call VOID "@cpu@_check_recovering_store"
! address (index-of (.sym regtype doublek)) 8 is_float))
profile
)
)
***************
*** 4627,4634 ****
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
! (.str name "$pack $" regtype "k,@($GRi,$GRj)")
! (+ pack (.sym regtype k) op GRi ope GRj)
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)
(set GRi address))
--- 4640,4647 ----
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
! (.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
! (+ pack (.sym regtype doublek) op GRi ope GRj)
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)
(set GRi address))
***************
*** 4864,4871 ****
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr)
! (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond")
! (+ pack (.sym regtype k) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)))
--- 4877,4884 ----
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr)
! (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond")
! (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)))
***************
*** 4933,4940 ****
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr)
! (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond")
! (+ pack (.sym regtype k) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)
--- 4946,4953 ----
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr)
! (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond")
! (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(sequence ((WI address))
(store-double-semantics mode regtype address GRj)
***************
*** 4988,4995 ****
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
! (.str name "$pack $" regtype "k,@($GRi,$d12)")
! (+ pack (.sym regtype k) op GRi d12)
(sequence ((WI address))
(store-double-semantics mode regtype address d12))
profile
--- 5001,5008 ----
(dni name
(comment)
((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
! (.str name "$pack $" regtype "doublek,@($GRi,$d12)")
! (+ pack (.sym regtype doublek) op GRi d12)
(sequence ((WI address))
(store-double-semantics mode regtype address d12))
profile
Index: sim/testsuite/sim/frv/testutils.inc
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/testsuite/sim/frv/testutils.inc,v
retrieving revision 1.23
diff -c -p -r1.23 testutils.inc
*** sim/testsuite/sim/frv/testutils.inc 27 Apr 2001 20:14:15 -0000 1.23
--- sim/testsuite/sim/frv/testutils.inc 10 Oct 2003 15:27:23 -0000
*************** nofsr0:
*** 97,102 ****
--- 97,112 ----
.endif
.endm
+ ; OR GR with immediate value
+ .macro or_gr_immed val reg
+ .if (\val >= -2048) && (\val <= 2047)
+ ori \reg,\val,\reg
+ .else
+ set_gr_immed \val,gr28
+ or \reg,gr28,\reg
+ .endif
+ .endm
+
; Set FR with another FR
.macro set_fr_fr src targ
fmovs \src,\targ
Index: sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs,v
retrieving revision 1.1
diff -c -p -r1.1 fp_exception-fr550.cgs
*** sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs 2 Oct 2003 21:09:04 -0000 1.1
--- sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs 10 Oct 2003 15:27:23 -0000
*************** align:
*** 16,21 ****
--- 16,39 ----
set_gr_addr pack,gr10
flush_data_cache gr10
+ ; Make the the source register number odd at badst. We can't simply
+ ; code an odd register number because the assembler will catch the
+ ; error.
+ set_gr_mem badst,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,badst
+ set_gr_addr badst,gr10
+ flush_data_cache gr10
+
+ ; Make the the dest register number odd at badld. We can't simply
+ ; code an odd register number because the assembler will catch the
+ ; error.
+ set_gr_mem badld,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,badld
+ set_gr_addr badld,gr10
+ flush_data_cache gr10
+
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x070,gr17 ; address of exception handler
*************** align:
*** 32,44 ****
set_spr_addr ok3,lr
set_gr_immed 4,gr20 ; PC increment
! badst1: stdfi fr1,@(sp,0) ; misaligned reg -- slot I0
test_gr_immed 1,gr15
set_spr_addr ok4,lr
set_gr_immed 8,gr20 ; PC increment
nop.p
! badst2: lddfi @(sp,0),fr9 ; misaligned reg -- slot I1
test_gr_immed 2,gr15
set_spr_addr ok5,lr
--- 50,62 ----
set_spr_addr ok3,lr
set_gr_immed 4,gr20 ; PC increment
! badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0
test_gr_immed 1,gr15
set_spr_addr ok4,lr
set_gr_immed 8,gr20 ; PC increment
nop.p
! badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1
test_gr_immed 2,gr15
set_spr_addr ok5,lr
Index: sim/testsuite/sim/frv/interrupts/fp_exception.cgs
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/testsuite/sim/frv/interrupts/fp_exception.cgs,v
retrieving revision 1.14
diff -c -p -r1.14 fp_exception.cgs
*** sim/testsuite/sim/frv/interrupts/fp_exception.cgs 2 Oct 2003 21:09:04 -0000 1.14
--- sim/testsuite/sim/frv/interrupts/fp_exception.cgs 10 Oct 2003 15:27:23 -0000
*************** align:
*** 16,21 ****
--- 16,39 ----
set_gr_addr pack,gr10
flush_data_cache gr10
+ ; Make the the source register number odd at badst. We can't simply
+ ; code an odd register number because the assembler will catch the
+ ; error.
+ set_gr_mem badst,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,badst
+ set_gr_addr badst,gr10
+ flush_data_cache gr10
+
+ ; Make the the dest register number odd at ld. We can't simply
+ ; code an odd register number because the assembler will catch the
+ ; error.
+ set_gr_mem badld,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,badld
+ set_gr_addr badld,gr10
+ flush_data_cache gr10
+
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x070,gr17 ; address of exception handler
*************** align:
*** 31,42 ****
set_gr_immed 0,gr15
set_spr_addr ok3,lr
! stdfi fr1,@(sp,0) ; misaligned reg -- slot I0
test_gr_immed 1,gr15
set_spr_addr ok4,lr
nop.p
! lddfi @(sp,0),fr9 ; misaligned reg -- slot I1
test_gr_immed 2,gr15
set_spr_addr ok5,lr
--- 49,60 ----
set_gr_immed 0,gr15
set_spr_addr ok3,lr
! badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0
test_gr_immed 1,gr15
set_spr_addr ok4,lr
nop.p
! badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1
test_gr_immed 2,gr15
set_spr_addr ok5,lr
Index: sim/testsuite/sim/frv/interrupts/regalign.cgs
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/testsuite/sim/frv/interrupts/regalign.cgs,v
retrieving revision 1.4
diff -c -p -r1.4 regalign.cgs
*** sim/testsuite/sim/frv/interrupts/regalign.cgs 2 Mar 2000 09:53:20 -0000 1.4
--- sim/testsuite/sim/frv/interrupts/regalign.cgs 10 Oct 2003 15:27:23 -0000
*************** align:
*** 16,39 ****
set_spr_addr ok1,lr
set_psr_et 1
set_gr_immed 4,gr20 ; PC increment
set_gr_immed 0,gr15
inc_gr_immed -12,sp ; for memory alignment
set_gr_addr bad1,gr17
! bad1: stdi gr1,@(sp,0) ; misaligned reg
test_gr_immed 1,gr15
set_gr_addr bad2,gr17
! bad2: lddi @(sp,0),gr9 ; misaligned reg
test_gr_immed 2,gr15
set_gr_addr bad3,gr17
! bad3: stdc cpr1,@(sp,gr0) ; misaligned reg
test_gr_immed 3,gr15
set_gr_addr bad4,gr17
! bad4: lddc @(sp,gr0),cpr9 ; misaligned reg
test_gr_immed 4,gr15
set_gr_addr bad5,gr17
--- 16,73 ----
set_spr_addr ok1,lr
set_psr_et 1
+ ; Make the the register number odd at bad[1-4], bad9 and bada.
+ ; We can't simply code an odd register number because the assembler
+ ; will catch the error.
+ set_gr_mem bad1,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,bad1
+ set_gr_addr bad1,gr10
+ flush_data_cache gr10
+ set_gr_mem bad2,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,bad2
+ set_gr_addr bad2,gr10
+ flush_data_cache gr10
+ set_gr_mem bad3,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,bad3
+ set_gr_addr bad3,gr10
+ flush_data_cache gr10
+ set_gr_mem bad4,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,bad4
+ set_gr_addr bad4,gr10
+ flush_data_cache gr10
+ set_gr_mem bad9,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,bad9
+ set_gr_addr bad9,gr10
+ flush_data_cache gr10
+ set_gr_mem bada,gr10
+ or_gr_immed 0x02000000,gr10
+ set_mem_gr gr10,bada
+ set_gr_addr bada,gr10
+ flush_data_cache gr10
+
set_gr_immed 4,gr20 ; PC increment
set_gr_immed 0,gr15
inc_gr_immed -12,sp ; for memory alignment
set_gr_addr bad1,gr17
! bad1: stdi gr0,@(sp,0) ; misaligned reg
test_gr_immed 1,gr15
set_gr_addr bad2,gr17
! bad2: lddi @(sp,0),gr8 ; misaligned reg
test_gr_immed 2,gr15
set_gr_addr bad3,gr17
! bad3: stdc cpr0,@(sp,gr0) ; misaligned reg
test_gr_immed 3,gr15
set_gr_addr bad4,gr17
! bad4: lddc @(sp,gr0),cpr8 ; misaligned reg
test_gr_immed 4,gr15
set_gr_addr bad5,gr17
*************** bad8: ldqc @(sp,gr0),cpr10 ; misaligned
*** 54,64 ****
set_gr_immed 0,gr20 ; PC increment
set_gr_addr bad9,gr17
! bad9: stdfi fr1,@(sp,0) ; misaligned reg
test_gr_immed 9,gr15
set_gr_addr bada,gr17
! bada: lddfi @(sp,0),fr9 ; misaligned reg
test_gr_immed 10,gr15
set_gr_addr badb,gr17
--- 88,98 ----
set_gr_immed 0,gr20 ; PC increment
set_gr_addr bad9,gr17
! bad9: stdfi fr0,@(sp,0) ; misaligned reg
test_gr_immed 9,gr15
set_gr_addr bada,gr17
! bada: lddfi @(sp,0),fr8 ; misaligned reg
test_gr_immed 10,gr15
set_gr_addr badb,gr17
Index: gas/testsuite/gas/frv/allinsn.d
===================================================================
RCS file: /cvs/cvsfiles/devo/gas/testsuite/gas/frv/allinsn.d,v
retrieving revision 1.3
diff -c -p -r1.3 allinsn.d
*** gas/testsuite/gas/frv/allinsn.d 29 Sep 2003 20:09:07 -0000 1.3
--- gas/testsuite/gas/frv/allinsn.d 10 Oct 2003 18:30:27 -0000
*************** Disassembly of section .text:
*** 37,46 ****
24: 82 04 13 c1 nudiv sp,sp,sp
00000028 <smul>:
! 28: 82 00 12 01 smul sp,sp,sp
0000002c <umul>:
! 2c: 82 00 12 81 umul sp,sp,sp
00000030 <sll>:
30: 82 04 12 01 sll sp,sp,sp
--- 37,46 ----
24: 82 04 13 c1 nudiv sp,sp,sp
00000028 <smul>:
! 28: 84 00 22 02 smul fp,fp,fp
0000002c <umul>:
! 2c: 84 00 22 82 umul fp,fp,fp
00000030 <sll>:
30: 82 04 12 01 sll sp,sp,sp
*************** Disassembly of section .text:
*** 76,82 ****
58: 83 68 00 c1 cnot sp,sp,cc0,0x0
0000005c <csmul>:
! 5c: 83 60 10 81 csmul sp,sp,sp,cc0,0x0
00000060 <csdiv>:
60: 83 60 10 c1 csdiv sp,sp,sp,cc0,0x0
--- 76,82 ----
58: 83 68 00 c1 cnot sp,sp,cc0,0x0
0000005c <csmul>:
! 5c: 85 60 20 82 csmul fp,fp,fp,cc0,0x0
00000060 <csdiv>:
60: 83 60 10 c1 csdiv sp,sp,sp,cc0,0x0
*************** Disassembly of section .text:
*** 118,127 ****
90: 82 04 13 41 sracc sp,sp,sp,icc0
00000094 <smulcc>:
! 94: 82 00 12 41 smulcc sp,sp,sp,icc0
00000098 <umulcc>:
! 98: 82 00 12 c1 umulcc sp,sp,sp,icc0
0000009c <caddcc>:
9c: 83 64 10 01 caddcc sp,sp,sp,cc0,0x0
--- 118,127 ----
90: 82 04 13 41 sracc sp,sp,sp,icc0
00000094 <smulcc>:
! 94: 84 00 22 42 smulcc fp,fp,fp,icc0
00000098 <umulcc>:
! 98: 84 00 22 c2 umulcc fp,fp,fp,icc0
0000009c <caddcc>:
9c: 83 64 10 01 caddcc sp,sp,sp,cc0,0x0
*************** Disassembly of section .text:
*** 130,136 ****
a0: 83 64 10 41 csubcc sp,sp,sp,cc0,0x0
000000a4 <csmulcc>:
! a4: 83 64 10 81 csmulcc sp,sp,sp,cc0,0x0
000000a8 <candcc>:
a8: 83 6c 10 01 candcc sp,sp,sp,cc0,0x0
--- 130,136 ----
a0: 83 64 10 41 csubcc sp,sp,sp,cc0,0x0
000000a4 <csmulcc>:
! a4: 85 64 20 82 csmulcc fp,fp,fp,cc0,0x0
000000a8 <candcc>:
a8: 83 6c 10 01 candcc sp,sp,sp,cc0,0x0
*************** Disassembly of section .text:
*** 190,199 ****
f0: 82 bc 10 00 nudivi sp,0,sp
000000f4 <smuli>:
! f4: 82 60 10 00 smuli sp,0,sp
000000f8 <umuli>:
! f8: 82 68 10 00 umuli sp,0,sp
000000fc <slli>:
fc: 82 a0 10 00 slli sp,0,sp
--- 190,199 ----
f0: 82 bc 10 00 nudivi sp,0,sp
000000f4 <smuli>:
! f4: 84 60 20 00 smuli fp,0,fp
000000f8 <umuli>:
! f8: 84 68 20 00 umuli fp,0,fp
000000fc <slli>:
fc: 82 a0 10 00 slli sp,0,sp
*************** Disassembly of section .text:
*** 223,232 ****
11c: 82 94 10 00 xoricc sp,0,sp,icc0
00000120 <smulicc>:
! 120: 82 64 10 00 smulicc sp,0,sp,icc0
00000124 <umulicc>:
! 124: 82 6c 10 00 umulicc sp,0,sp,icc0
00000128 <sllicc>:
128: 82 a4 10 00 sllicc sp,0,sp,icc0
--- 223,232 ----
11c: 82 94 10 00 xoricc sp,0,sp,icc0
00000120 <smulicc>:
! 120: 84 64 20 00 smulicc fp,0,fp,icc0
00000124 <umulicc>:
! 124: 84 6c 20 00 umulicc fp,0,fp,icc0
00000128 <sllicc>:
128: 82 a4 10 00 sllicc sp,0,sp,icc0
*************** Disassembly of section .text:
*** 310,316 ****
190: 80 08 1a 81 nldf @\(sp,sp\),fr0
00000194 <ldd>:
! 194: 82 08 11 41 ldd @\(sp,sp\),sp
00000198 <lddf>:
198: 80 08 12 c1 lddf @\(sp,sp\),fr0
--- 310,316 ----
190: 80 08 1a 81 nldf @\(sp,sp\),fr0
00000194 <ldd>:
! 194: 84 08 11 41 ldd @\(sp,sp\),fp
00000198 <lddf>:
198: 80 08 12 c1 lddf @\(sp,sp\),fr0
*************** Disassembly of section .text:
*** 319,325 ****
19c: 80 08 13 81 lddc @\(sp,sp\),cpr0
000001a0 <nldd>:
! 1a0: 82 08 19 41 nldd @\(sp,sp\),sp
000001a4 <nlddf>:
1a4: 80 08 1a c1 nlddf @\(sp,sp\),fr0
--- 319,325 ----
19c: 80 08 13 81 lddc @\(sp,sp\),cpr0
000001a0 <nldd>:
! 1a0: 84 08 19 41 nldd @\(sp,sp\),fp
000001a4 <nlddf>:
1a4: 80 08 1a c1 nlddf @\(sp,sp\),fr0
*************** Disassembly of section .text:
*** 391,400 ****
1fc: 80 08 1e 81 nldfu @\(sp,sp\),fr0
00000200 <lddu>:
! 200: 82 08 15 41 lddu @\(sp,sp\),sp
00000204 <nlddu>:
! 204: 82 08 1d 41 nlddu @\(sp,sp\),sp
00000208 <lddfu>:
208: 80 08 16 c1 lddfu @\(sp,sp\),fr0
--- 391,400 ----
1fc: 80 08 1e 81 nldfu @\(sp,sp\),fr0
00000200 <lddu>:
! 200: 84 08 15 41 lddu @\(sp,sp\),fp
00000204 <nlddu>:
! 204: 84 08 1d 41 nlddu @\(sp,sp\),fp
00000208 <lddfu>:
208: 80 08 16 c1 lddfu @\(sp,sp\),fr0
*************** Disassembly of section .text:
*** 469,481 ****
264: 81 28 10 00 nldfi @\(sp,0\),fr0
00000268 <lddi>:
! 268: 82 cc 10 00 lddi @\(sp,0\),sp
0000026c <lddfi>:
26c: 80 ec 10 00 lddfi @\(sp,0\),fr0
00000270 <nlddi>:
! 270: 83 14 10 00 nlddi @\(sp,0\),sp
00000274 <nlddfi>:
274: 81 2c 10 00 nlddfi @\(sp,0\),fr0
--- 469,481 ----
264: 81 28 10 00 nldfi @\(sp,0\),fr0
00000268 <lddi>:
! 268: 84 cc 10 00 lddi @\(sp,0\),fp
0000026c <lddfi>:
26c: 80 ec 10 00 lddfi @\(sp,0\),fr0
00000270 <nlddi>:
! 270: 85 14 10 00 nlddi @\(sp,0\),fp
00000274 <nlddfi>:
274: 81 2c 10 00 nlddfi @\(sp,0\),fr0
*************** Disassembly of section .text:
*** 532,538 ****
2b8: 80 0c 1a 81 rstf fr0,@\(sp,sp\)
000002bc <std>:
! 2bc: 82 0c 10 c1 std sp,@\(sp,sp\)
000002c0 <stdf>:
2c0: 80 0c 12 c1 stdf fr0,@\(sp,sp\)
--- 532,538 ----
2b8: 80 0c 1a 81 rstf fr0,@\(sp,sp\)
000002bc <std>:
! 2bc: 84 0c 10 c1 std fp,@\(sp,sp\)
000002c0 <stdf>:
2c0: 80 0c 12 c1 stdf fr0,@\(sp,sp\)
*************** Disassembly of section .text:
*** 541,547 ****
2c4: 80 0c 19 81 stdc cpr0,@\(sp,sp\)
000002c8 <rstd>:
! 2c8: 82 0c 18 c1 rstd sp,@\(sp,sp\)
000002cc <rstdf>:
2cc: 80 0c 1a c1 rstdf fr0,@\(sp,sp\)
--- 541,547 ----
2c4: 80 0c 19 81 stdc cpr0,@\(sp,sp\)
000002c8 <rstd>:
! 2c8: 84 0c 18 c1 rstd fp,@\(sp,sp\)
000002cc <rstdf>:
2cc: 80 0c 1a c1 rstdf fr0,@\(sp,sp\)
*************** Disassembly of section .text:
*** 583,589 ****
2fc: 80 0c 1b 41 stcu cpr0,@\(sp,sp\)
00000300 <stdu>:
! 300: 82 0c 14 c1 stdu sp,@\(sp,sp\)
00000304 <stdfu>:
304: 80 0c 16 c1 stdfu fr0,@\(sp,sp\)
--- 583,589 ----
2fc: 80 0c 1b 41 stcu cpr0,@\(sp,sp\)
00000300 <stdu>:
! 300: 84 0c 14 c1 stdu fp,@\(sp,sp\)
00000304 <stdfu>:
304: 80 0c 16 c1 stdfu fr0,@\(sp,sp\)
*************** Disassembly of section .text:
*** 625,631 ****
334: 81 80 10 81 cldf @\(sp,sp\),fr0,cc0,0x0
00000338 <cldd>:
! 338: 83 7c 10 41 cldd @\(sp,sp\),sp,cc0,0x0
0000033c <clddf>:
33c: 81 80 10 c1 clddf @\(sp,sp\),fr0,cc0,0x0
--- 625,631 ----
334: 81 80 10 81 cldf @\(sp,sp\),fr0,cc0,0x0
00000338 <cldd>:
! 338: 85 7c 10 41 cldd @\(sp,sp\),fp,cc0,0x0
0000033c <clddf>:
33c: 81 80 10 c1 clddf @\(sp,sp\),fr0,cc0,0x0
*************** Disassembly of section .text:
*** 658,664 ****
360: 81 8c 10 81 cldfu @\(sp,sp\),fr0,cc0,0x0
00000364 <clddu>:
! 364: 83 88 10 41 clddu @\(sp,sp\),sp,cc0,0x0
00000368 <clddfu>:
368: 81 8c 10 c1 clddfu @\(sp,sp\),fr0,cc0,0x0
--- 658,664 ----
360: 81 8c 10 81 cldfu @\(sp,sp\),fr0,cc0,0x0
00000364 <clddu>:
! 364: 85 88 10 41 clddu @\(sp,sp\),fp,cc0,0x0
00000368 <clddfu>:
368: 81 8c 10 c1 clddfu @\(sp,sp\),fr0,cc0,0x0
*************** Disassembly of section .text:
*** 685,691 ****
384: 81 98 10 81 cstf fr0,@\(sp,sp\),cc0,0x0
00000388 <cstd>:
! 388: 83 90 10 c1 cstd sp,@\(sp,sp\),cc0,0x0
0000038c <cstdf>:
38c: 81 98 10 c1 cstdf fr0,@\(sp,sp\),cc0,0x0
--- 685,691 ----
384: 81 98 10 81 cstf fr0,@\(sp,sp\),cc0,0x0
00000388 <cstd>:
! 388: 85 90 10 c1 cstd fp,@\(sp,sp\),cc0,0x0
0000038c <cstdf>:
38c: 81 98 10 c1 cstdf fr0,@\(sp,sp\),cc0,0x0
*************** Disassembly of section .text:
*** 712,718 ****
3a8: 81 a0 10 81 cstfu fr0,@\(sp,sp\),cc0,0x0
000003ac <cstdu>:
! 3ac: 83 9c 10 c1 cstdu sp,@\(sp,sp\),cc0,0x0
000003b0 <cstdfu>:
3b0: 81 a0 10 c1 cstdfu fr0,@\(sp,sp\),cc0,0x0
--- 712,718 ----
3a8: 81 a0 10 81 cstfu fr0,@\(sp,sp\),cc0,0x0
000003ac <cstdu>:
! 3ac: 85 9c 10 c1 cstdu fp,@\(sp,sp\),cc0,0x0
000003b0 <cstdfu>:
3b0: 81 a0 10 c1 cstdfu fr0,@\(sp,sp\),cc0,0x0
*************** Disassembly of section .text:
*** 736,742 ****
3c8: 81 54 10 00 stfi fr0,@\(sp,0\)
000003cc <stdi>:
! 3cc: 83 4c 10 00 stdi sp,@\(sp,0\)
000003d0 <stdfi>:
3d0: 81 58 10 00 stdfi fr0,@\(sp,0\)
--- 736,742 ----
3c8: 81 54 10 00 stfi fr0,@\(sp,0\)
000003cc <stdi>:
! 3cc: 85 4c 10 00 stdi fp,@\(sp,0\)
000003d0 <stdfi>:
3d0: 81 58 10 00 stdfi fr0,@\(sp,0\)
Index: gas/testsuite/gas/frv/allinsn.s
===================================================================
RCS file: /cvs/cvsfiles/devo/gas/testsuite/gas/frv/allinsn.s,v
retrieving revision 1.3
diff -c -p -r1.3 allinsn.s
*** gas/testsuite/gas/frv/allinsn.s 29 Sep 2003 20:09:07 -0000 1.3
--- gas/testsuite/gas/frv/allinsn.s 10 Oct 2003 18:30:27 -0000
*************** nudiv:
*** 45,55 ****
.text
.global smul
smul:
! smul sp,sp,sp
.text
.global umul
umul:
! umul sp,sp,sp
.text
.global sll
sll:
--- 45,55 ----
.text
.global smul
smul:
! smul fp,fp,fp
.text
.global umul
umul:
! umul fp,fp,fp
.text
.global sll
sll:
*************** cnot:
*** 97,103 ****
.text
.global csmul
csmul:
! csmul sp,sp,sp,cc0,0
.text
.global csdiv
csdiv:
--- 97,103 ----
.text
.global csmul
csmul:
! csmul fp,fp,fp,cc0,0
.text
.global csdiv
csdiv:
*************** sracc:
*** 153,163 ****
.text
.global smulcc
smulcc:
! smulcc sp,sp,sp,icc0
.text
.global umulcc
umulcc:
! umulcc sp,sp,sp,icc0
.text
.global caddcc
caddcc:
--- 153,163 ----
.text
.global smulcc
smulcc:
! smulcc fp,fp,fp,icc0
.text
.global umulcc
umulcc:
! umulcc fp,fp,fp,icc0
.text
.global caddcc
caddcc:
*************** csubcc:
*** 169,175 ****
.text
.global csmulcc
csmulcc:
! csmulcc sp,sp,sp,cc0,0
.text
.global candcc
candcc:
--- 169,175 ----
.text
.global csmulcc
csmulcc:
! csmulcc fp,fp,fp,cc0,0
.text
.global candcc
candcc:
*************** nudivi:
*** 249,259 ****
.text
.global smuli
smuli:
! smuli sp,0,sp
.text
.global umuli
umuli:
! umuli sp,0,sp
.text
.global slli
slli:
--- 249,259 ----
.text
.global smuli
smuli:
! smuli fp,0,fp
.text
.global umuli
umuli:
! umuli fp,0,fp
.text
.global slli
slli:
*************** xoricc:
*** 293,303 ****
.text
.global smulicc
smulicc:
! smulicc sp,0,sp,icc0
.text
.global umulicc
umulicc:
! umulicc sp,0,sp,icc0
.text
.global sllicc
sllicc:
--- 293,303 ----
.text
.global smulicc
smulicc:
! smulicc fp,0,fp,icc0
.text
.global umulicc
umulicc:
! umulicc fp,0,fp,icc0
.text
.global sllicc
sllicc:
*************** nldf:
*** 409,415 ****
.text
.global ldd
ldd:
! ldd @(sp,sp),sp
.text
.global lddf
lddf:
--- 409,415 ----
.text
.global ldd
ldd:
! ldd @(sp,sp),fp
.text
.global lddf
lddf:
*************** lddc:
*** 421,427 ****
.text
.global nldd
nldd:
! nldd @(sp,sp),sp
.text
.global nlddf
nlddf:
--- 421,427 ----
.text
.global nldd
nldd:
! nldd @(sp,sp),fp
.text
.global nlddf
nlddf:
*************** nldfu:
*** 517,527 ****
.text
.global lddu
lddu:
! lddu @(sp,sp),sp
.text
.global nlddu
nlddu:
! nlddu @(sp,sp),sp
.text
.global lddfu
lddfu:
--- 517,527 ----
.text
.global lddu
lddu:
! lddu @(sp,sp),fp
.text
.global nlddu
nlddu:
! nlddu @(sp,sp),fp
.text
.global lddfu
lddfu:
*************** nldfi:
*** 621,627 ****
.text
.global lddi
lddi:
! lddi @(sp,0),sp
.text
.global lddfi
lddfi:
--- 621,627 ----
.text
.global lddi
lddi:
! lddi @(sp,0),fp
.text
.global lddfi
lddfi:
*************** lddfi:
*** 629,635 ****
.text
.global nlddi
nlddi:
! nlddi @(sp,0),sp
.text
.global nlddfi
nlddfi:
--- 629,635 ----
.text
.global nlddi
nlddi:
! nlddi @(sp,0),fp
.text
.global nlddfi
nlddfi:
*************** rstf:
*** 705,711 ****
.text
.global std
std:
! std sp,@(sp,sp)
.text
.global stdf
stdf:
--- 705,711 ----
.text
.global std
std:
! std fp,@(sp,sp)
.text
.global stdf
stdf:
*************** stdc:
*** 717,723 ****
.text
.global rstd
rstd:
! rstd sp,@(sp,sp)
.text
.global rstdf
rstdf:
--- 717,723 ----
.text
.global rstd
rstd:
! rstd fp,@(sp,sp)
.text
.global rstdf
rstdf:
*************** stcu:
*** 773,779 ****
.text
.global stdu
stdu:
! stdu sp,@(sp,sp)
.text
.global stdfu
stdfu:
--- 773,779 ----
.text
.global stdu
stdu:
! stdu fp,@(sp,sp)
.text
.global stdfu
stdfu:
*************** cldf:
*** 829,835 ****
.text
.global cldd
cldd:
! cldd @(sp,sp),sp,cc0,0
.text
.global clddf
clddf:
--- 829,835 ----
.text
.global cldd
cldd:
! cldd @(sp,sp),fp,cc0,0
.text
.global clddf
clddf:
*************** cldfu:
*** 873,879 ****
.text
.global clddu
clddu:
! clddu @(sp,sp),sp,cc0,0
.text
.global clddfu
clddfu:
--- 873,879 ----
.text
.global clddu
clddu:
! clddu @(sp,sp),fp,cc0,0
.text
.global clddfu
clddfu:
*************** cstf:
*** 909,915 ****
.text
.global cstd
cstd:
! cstd sp,@(sp,sp),cc0,0
.text
.global cstdf
cstdf:
--- 909,915 ----
.text
.global cstd
cstd:
! cstd fp,@(sp,sp),cc0,0
.text
.global cstdf
cstdf:
*************** cstfu:
*** 945,951 ****
.text
.global cstdu
cstdu:
! cstdu sp,@(sp,sp),cc0,0
.text
.global cstdfu
cstdfu:
--- 945,951 ----
.text
.global cstdu
cstdu:
! cstdu fp,@(sp,sp),cc0,0
.text
.global cstdfu
cstdfu:
*************** stfi:
*** 977,983 ****
.text
.global stdi
stdi:
! stdi sp,@(sp,0)
.text
.global stdfi
stdfi:
--- 977,983 ----
.text
.global stdi
stdi:
! stdi fp,@(sp,0)
.text
.global stdfi
stdfi: