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[mips sim patch] remove check_branch_bug()/mark_branch_bug().
- From: cgd at broadcom dot com
- To: gdb-patches at sources dot redhat dot com
- Date: 16 Dec 2002 18:09:48 -0800
- Subject: [mips sim patch] remove check_branch_bug()/mark_branch_bug().
check_branch_bug() and mark_branch_bug() have been completely
un-documented nop-ops since the initial revisions of the mips sim code
in the 'sourceware' CVS repos.
Given that they do nothing and there is no indication that they
_should_ do something and/or what configuration they should do it on,
I'm inclined to remove them.
If a future simulator submission wants to reintroduce them, we can
consider them then.
I'm planning to check this in in about 24 hours unless there is much
screaming before then (unless something goes strangely wrong w/ the
test runs i'm currently doing 8-).
cgd
===================================================================
2002-12-16 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (check_branch_bug, mark_branch_bug): Remove.
* mips.igen: Remove all invocations of check_branch_bug and
mark_branch_bug.
Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.49
diff -u -F^[:01] -r1.49 mips.igen
--- mips.igen 31 Jul 2002 05:44:54 -0000 1.49
+++ mips.igen 17 Dec 2002 01:23:04 -0000
@@ -565,10 +565,8 @@ 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -588,10 +586,8 @@ 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -614,10 +610,8 @@ 000001,5.RS,00001,16.OFFSET:REGIMM:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -638,13 +632,11 @@ 000001,5.RS!31,10001,16.OFFSET:REGIMM:32
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -664,7 +656,6 @@ 000001,5.RS!31,10011,16.OFFSET:REGIMM:32
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
@@ -672,7 +663,6 @@ 000001,5.RS!31,10011,16.OFFSET:REGIMM:32
executed */
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -694,10 +684,8 @@ 000001,5.RS,00011,16.OFFSET:REGIMM:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -720,10 +708,8 @@ 000111,5.RS,00000,16.OFFSET:NORMAL:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -743,12 +729,10 @@ 010111,5.RS,00000,16.OFFSET:NORMAL:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -771,12 +755,10 @@ 000110,5.RS,00000,16.OFFSET:NORMAL:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -796,10 +778,8 @@ 010110,5.RS,00000,16.OFFSET:NORMAL:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -822,10 +802,8 @@ 000001,5.RS,00000,16.OFFSET:REGIMM:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -846,7 +824,6 @@ 000001,5.RS!31,10000,16.OFFSET:REGIMM:32
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
@@ -854,7 +831,6 @@ 000001,5.RS!31,10000,16.OFFSET:REGIMM:32
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -874,13 +850,11 @@ 000001,5.RS!31,10010,16.OFFSET:REGIMM:32
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -902,12 +876,10 @@ 000001,5.RS,00010,16.OFFSET:REGIMM:32::B
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -930,10 +902,8 @@ 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -953,10 +923,8 @@ 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -3792,13 +3760,11 @@ 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP
*mipsIII:
{
check_fpu (SD_);
- check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
if (PREVCOC1() == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
TRACE_BRANCH_RESULT (dest);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
@@ -3824,11 +3790,9 @@ 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:CO
*r3900:
{
check_fpu (SD_);
- check_branch_bug ();
if (GETFCC(CC) == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
Index: sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.23
diff -u -F^[:01] -r1.23 sim-main.h
--- sim-main.h 14 Jun 2002 18:49:09 -0000 1.23
+++ sim-main.h 17 Dec 2002 01:23:04 -0000
@@ -423,10 +423,6 @@
hilo_history lo_history;
#define LOHISTORY (&(CPU)->lo_history)
-#define check_branch_bug()
-#define mark_branch_bug(TARGET)
-
-
sim_cpu_base base;
};