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[patch/rfc]sim/ppc/ppc-instructions: implement a simple dcbz
- From: Julien Ducourthial <jducourt at noos dot fr>
- To: gdb-patches at sources dot redhat dot com
- Date: Tue, 18 Jun 2002 00:34:23 +0200
- Subject: [patch/rfc]sim/ppc/ppc-instructions: implement a simple dcbz
Hello,
With the ppc simulator all data cache related instructions are stubs.
It's not a problem (the data cache is not simulated), except for dcbz
(Data Cache Bloc set to Zero). This instruction should actually fill the
cache bloc (and thus the memory) with zeroes. Attached is a simple
implementation of dcbz. It works great for me ;), but has the following
limitations :
- it does not generate alignement exceptions, as do the actual
processors, when used with caching-inhibited or write-through memory
(note : the behaviour is not specified by the green book)
- it assumes 32 bytes cache blocs (ok for 603, 604, 750, 7400 but the
601 may be different).
Julien.
2002-06-15 Julien Ducourthial <jducourt@noos.fr>
* ppc-instructions (dcbz): Implement a simple dcbz.
Index: ppc-instructions
===================================================================
RCS file: /cvs/src/src/sim/ppc/ppc-instructions,v
retrieving revision 1.4
diff -c -p -r1.4 ppc-instructions
*** ppc-instructions 23 Mar 2002 21:18:31 -0000 1.4
--- ppc-instructions 17 Jun 2002 22:03:16 -0000
*************** void::function::invalid_zero_divide_oper
*** 4704,4715 ****
TRACE(trace_tbd,("Data Cache Block Touch for Store\n"));
PPC_INSN_INT(0, (RA_BITMASK & ~1) | RB_BITMASK, 0/*Rc*/);
! 0.31,6./,11.RA,16.RB,21.1014,31./:X:::Data Cache Block set to Zero
*601: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603: PPC_UNIT_LSU, PPC_UNIT_LSU, 10, 10, 0
*603e:PPC_UNIT_LSU, PPC_UNIT_LSU, 10, 10, 0
*604: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 3, 0
! TRACE(trace_tbd,("Data Cache Block set to Zero\n"));
PPC_INSN_INT(0, (RA_BITMASK & ~1) | RB_BITMASK, 0/*Rc*/);
0.31,6./,11.RA,16.RB,21.54,31./:X:::Data Cache Block Store
--- 4704,4726 ----
TRACE(trace_tbd,("Data Cache Block Touch for Store\n"));
PPC_INSN_INT(0, (RA_BITMASK & ~1) | RB_BITMASK, 0/*Rc*/);
! 0.31,6./,11.RA,16.RB,21.1014,31./:X::dcbz:Data Cache Block set to Zero
*601: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603: PPC_UNIT_LSU, PPC_UNIT_LSU, 10, 10, 0
*603e:PPC_UNIT_LSU, PPC_UNIT_LSU, 10, 10, 0
*604: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 3, 0
! unsigned_word b;
! unsigned_word EA;
! unsigned_word count ;
! if (RA_is_0) b = 0;
! else b = *rA ;
! EA = (b + *rB) & (~31U) ;
! count = 0 ;
! while (count < 8) {
! STORE(EA,4,0) ;
! EA = EA+4 ;
! count = count+1 ;
! }
PPC_INSN_INT(0, (RA_BITMASK & ~1) | RB_BITMASK, 0/*Rc*/);
0.31,6./,11.RA,16.RB,21.54,31./:X:::Data Cache Block Store