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Re: SH5 simulator contribution
>>>>> "Andrew" == Andrew Cagney <firstname.lastname@example.org> writes:
Andrew> Firstly, GDB already has an SH simululator that can be used to generate
Andrew> a sh1, sh2, sh3, sh3e, sh4 and sh-dsp (but only one at a time). Does
Andrew> this new simulator cover that set or only a subset? i.e. is it a drop
Andrew> in replacement?
It covers a subset. It will handle sh2, sh3, sh4 and sh5. In other
words, it is not (quite) yet able to replace the existing SH[1-4]
Andrew> Secondly, the MIPS, mn10300, d10v and other IGEN simulators support more
Andrew> than one cpu variant (can't use ISA - see binutils list :-/). How does
Andrew> this simulator go in this regard?
I'm afraid I'm going to need you to clarify the terminology. :-(