Re: sim/igen: add gen-delay-slot generation option

[Andrew Cagney <ac131313 at cygnus dot com>]

"Chris G. Demetriou" wrote:
> 
> The patch below:
> 
> (1) adds a new simulator generation option to igen, "gen-delay-slot".
> This new option generates PC pipe manipulation operations in a way
> that can be used to cleanly and correctly model MIPS branch delay
> slots.
> 
> (2) changes the generated code so that any wired-zero registers are
> cleared by common code (shared by all of the opcodes), rather than
> by each individual opcode's implementation.
> 
> The changes were implemented by a coworker, Ed Satterthwaite (who's
> CC'd on this message), then cleaned up for submission by me.  We've
> both got assignment paperwork on file.
> 
> I've tested this in the manner described in the message I recently
> sent:
> 
>         http://sources.redhat.com/ml/gdb/2000-12/msg00015.html
> 
> It doesn't change any test output for any of the targets there
> (several of which -- all but fr30 and sparclite -- seem to
> successfully run things through the resulting 'run' binaries).  This
> doesn't surprise me; as you would see by looking at the code, (1)
> doesn't change the code unless you've specified the new option, and
> (2) does changes the code in a fairly straightforward way.  8-)

Chris,

How does this relate to the existing gen-delay-branch used by the
TiC80.  You describe this as a variant so is it possible to consildate
the two and keep things simpler?  It is also hard to judge the change
without seeing what is being done to the sim/mips directory.

The TiC80 has a clasic (ie sparc like) delay slot architecture where the
two PC's are revealed.

This would only affect the igen simulators (tic80, d30v, mips, mn10300).

	Andrew