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[sim] mips cleanups.


Just FYI,

	Andrew
Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (MxC1, DMxC1): Fix printf formatting.

Index: mips.igen
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/mips/mips.igen,v
retrieving revision 1.83
diff -p -r1.83 mips.igen
*** mips.igen	2000/06/16 21:08:19	1.83
--- mips.igen	2000/06/23 12:36:27
***************
*** 6648,6655 ****
  	{
  	  if (STATE_VERBOSE_P(SD))
  	    sim_io_eprintf (SD, 
! 	      "Warning: PC 0x%x: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
! 	      CIA);
  	  PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
  	}
      }
--- 6648,6655 ----
  	{
  	  if (STATE_VERBOSE_P(SD))
  	    sim_io_eprintf (SD, 
! 	      "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
! 	      (long) CIA);
  	  PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
  	}
      }
***************
*** 6991,6997 ****
  	{
  	  if (STATE_VERBOSE_P(SD))
  	    sim_io_eprintf (SD, 
! 	      "Warning:  PC 0x%x: MTC1 not DMTC1 with 64 bit regs\n", CIA);
  	  PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
  	}
        else
--- 6991,6998 ----
  	{
  	  if (STATE_VERBOSE_P(SD))
  	    sim_io_eprintf (SD, 
! 			    "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
! 			    (long) CIA);
  	  PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
  	}
        else

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