Re: Unifying i387 support

[jtc@redback.com (J.T. Conklin)]

jtc> I think Eli was asking whether it would be better to use the FXSAVE
jtc> format introduced with MMX and extended with the SSE instead of the
jtc> FSAVE format described above.  It might be worth doing if we're 
jtc> going to support MMX and SSE registers.  

Jim> My Pentium manual predates MMX, so I can't really comment much on
Jim> this.  

Time to get a new pentium manual.  You can download pdf's of the three
volume IA32 Software Development Manual from developer.intel.com.

Jim> It looks like the FXSAVE instruction saves the floating-point
Jim> registers separately from the XMM registers; doesn't that mean
Jim> it's saving the same bits twice?

Not quite.  

The MMX registers (MM0-MM7) overlay the FP registers (ST- ST7) in both
the FSAVE and FXSAVE formats.  But the SSE registers (XMM0-XMM7) which
were introduced with the Pentium III are stored separately in the
FXSAVE format.

Jim> As I understand it, there are multiple ways to interpret the contents
Jim> of an MMX register.  It might contain one double, or two floats.  

A MMX register might contain packed bytes (8x8 bits), packed words (4x
16 bits), packed doublewords (2x32 bits) or one quadword (64 bits), or
when in FP mode an 80-bit FP value.  A SSE register contains 4
single-precision (32-bit) floats.
p
Jim> And only the user knows what is appropriate at any given time.  I
Jim> can't tell if this impinges on our choice of register layout.
Jim> Does anyone have any idea how to handle this?

This is similar to the general purpose registers: EAX, AX, AH, and AL
overlap, and I don't think there are separate register numbers for
them (although one could argue that there should be, since AL and AH
can hold two different variables simultaneously).

But unlike the general purpose registers, the MMX / SSE registers
operate on a whole bank at a time.

	--jtc

-- 
J.T. Conklin
RedBack Networks