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sh-stub.c: single-stepping support for branch-far instructions
- To: gdb-patches@sourceware.cygnus.com
- Subject: sh-stub.c: single-stepping support for branch-far instructions
- From: Jesper Skov <jskov@cygnus.co.uk>
- Date: Fri, 9 Jul 1999 13:08:06 +0100
- Resent-To: gdb-patches@sourceware.cygnus.com
The below patch adds single-stepping support for the bsrf and braf
instructions of the SH2/3.
Jesper
Index: ChangeLog
===================================================================
RCS file: /cvs/cvsfiles/devo/gdb/ChangeLog,v
retrieving revision 1.5008
diff -u -r1.5008 ChangeLog
--- ChangeLog 1999/05/25 06:28:13 1.5008
+++ ChangeLog 1999/07/09 11:58:28
@@ -1,3 +1,7 @@
+1999-07-09 Jesper Skov <jskov@cygnus.co.uk>
+
+ * sh-stub.c (doSStep): Added handling of branch-far instructions.
+
Tue May 25 16:18:25 1999 Andrew Cagney <cagney@amy.cygnus.com>
* remote-d10v.c (d10v_eva_prepare_to_trace,
Index: sh-stub.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gdb/sh-stub.c,v
retrieving revision 2.4
diff -u -r2.4 sh-stub.c
--- sh-stub.c 1999/05/11 22:23:34 2.4
+++ sh-stub.c 1999/07/09 11:58:29
@@ -170,6 +170,7 @@
#define RTE_INSTR 0x002b
#define TRAPA_INSTR 0xc300
#define SSTEP_INSTR 0xc3ff
+#define BxxF_INSTR 0x0003
/* Hitachi SH processor register masks */
@@ -557,7 +558,15 @@
opcode = *instrMem;
stepped = 1;
- if ((opcode & COND_BR_MASK) == BT_INSTR)
+ if ((opcode & UCOND_RBR_MASK) == BxxF_INSTR) {
+ reg = (char) ((opcode & UCOND_REG) >> 8);
+ displacement = get_register(reg);
+ instrMem = (short *) (pc + displacement + 4);
+ /*
+ * Remember PC points to second instr.
+ * after PC of branch ... so add 4
+ */
+ } else if ((opcode & COND_BR_MASK) == BT_INSTR)
{
if (registers[SR] & T_BIT_MASK)
{