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Re: Cortex-M1/3 SysTick/RTC wrote:
Andrew Lunn wrote:
SysTick is great for the eCos clock.

You could do a very simple HAL_DELAY_US(us) which only has 1ms
resolution. Not great, but it at least will work and gets you going.

Or you can go for implementation 3, using a 1ms calibration time
derived from the SysTick.

I have implemented the real-time-clock using the SysTick. It should work pretty well as I found out with some simple tests. I have also used the SysTick counter for a default implementation of the HAL_DELAY_US function, which should be pretty accurate (0.01 us accuracy with 72mhz clock). What bothers me though, is how to implement the SysTick interrupt. It belongs to the default exception vectors of the Cortex core. So I guess the architecture should define this ISR vector, but normally these go into the variant or platform packages. How can we do that?

Did some more reading on the exception and interrupt handling on the cortex. The cortex architecture defines the first 16 exception vectors by default. The SysTick interrupt belongs to these first 16 vectors. Variants may implement up to 240 interrupts, which follow the first 16 exception vectors. Unfortunately, register for enabling/disabling, priority etc. of the exception vectors are not linear for both the 16 system vectors and the interrupt vectors. If the SysTick should be usable as a normal interrupt source, it will be the "only" special case. How can, or should that be implemented efficiently? Any ideas?


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