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Re: Re: Adder II (MPC852T), issue while migrating to 32MB memory
On 18-Jul-06, at 08:24 , Gary Thomas wrote:
Andre-John Mas wrote:
I have a collegue who suspects that we may need to be changing this
block too, in adder.S
//#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)
+31)/32)&0xFF)
lwi r3,0x00802114|(MAMR_PTA<<24)
stw r3,MAMR(r4)
stw r3,MBMR(r4)
what should this be changed to if this is indeed the case?
This register has nothing to do with addressing - only timing.
I talked the colleague and he said the reason he suggested it was
because he
though it might be a timing issue in accessing the memory.
Did you change the OR1 register as I suggested?
Yes I did. We can boot and reference the address. Before we would
crash if we did that.
The only thing is with the test case in the previous post, I am not
sure that we are
really accessing the second portion of the ROM. It seems to suggest
that we are accessing
the bottom 16MB as if it were both the bottom and top halves.
Andre
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