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RE: about porting ecos in S3C4510B development board
- From: "Hu Ying" <ying_hu at alliedtelesyn dot com>
- To: "'Jonathan Larmour'" <jifl at eCosCentric dot com>
- Cc: <ecos-discuss at sources dot redhat dot com>
- Date: Wed, 11 Feb 2004 14:24:08 +0800
- Subject: RE: [ECOS] about porting ecos in S3C4510B development board
- Reply-to: <ying_hu at alliedtelesyn dot com>
I am following the step-by-step instructions stated in
http://www4.ncsu.edu:8030/~abdudani/ecos/docs/hal-porting-platform.html
1. I copied the all files/directories in the hal/arm/SNDS into a new folder
which I name as /hal/arm/test.
2. I changed the name of the following files:
subdirectory cdl
hal_arm_snds.cdl -> hal_arm_test.cdl
subdirectory include\pkgconf
mlt_arm_snds_ram.h -> mlt_arm_test_ram.h
mlt_arm_snds_rom.h -> mlt_arm_test_rom.h
mlt_arm_snds_ram.ldi -> mlt_arm_test_ram.ldi
mlt_arm_snds_rom.ldi -> mlt_arm_test_rom.ldi
3. I add the package and target descriptions to ecos.db
package CYGPKG_HAL_ARM_TEST {
alias { "TEST" hal_arm_test arm_test_hal}
directory hal/arm/test
script hal_arm_test.cdl
hardware
description "
The S3C4510B TEST package provides the support needed to run eCos
on a
Samsung S3C4510B TEST board"
}
target test {
alias { "S3C4510B TEST" TEST test test100 }
packages { CYGPKG_HAL_ARM
CYGPKG_HAL_ARM_TEST
}
##enable { CYGHWR_HAL_ARM_BIGENDIAN } // BIGENDIAN is disabled
because my board is LITTLEENDIAN
description "
The test target provides the packages needed to run eCos on a
S3C4510B TEST board."
}
4. I modified the hal_arm_test.cdl and the .mlt .h files for the memory
layout:
****************************************************************************
*****************************
*******hal_arm_test.cdl:
******* basically I just replace the "snds" with "test"************
****************************************************************************
*****************************
cdl_package CYGPKG_HAL_ARM_TEST {
display "S3C4510B TEST Evaluation Board"
parent CYGPKG_HAL_ARM
define_header hal_arm_test.h
include_dir cyg/hal
hardware
description "
The S3C4510B TEST HAL package provides the support needed to run
eCos on a S3C4510B TEST board"
compile hal_diag.c test_misc.c
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_ARM_ARCH_ARM7
implements CYGINT_HAL_ARM_THUMB_ARCH
# FIXME: Add endian option
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H
<pkgconf/hal_arm.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H
<pkgconf/hal_arm_test.h>"
puts $::cdl_header ""
puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM 7TDMI\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"S3C4510B TEST\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
puts $::cdl_header ""
}
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the S3C4510B TEST board it is possible to build
the system for either RAM bootstrap or ROM bootstrap.
RAM bootstrap generally requires that the board
is equipped with ROMs containing a suitable ROM monitor or
equivalent software that allows GDB to download the eCos
application on to the board. The ROM bootstrap typically
requires that the eCos application be blown into EPROMs or
equivalent technology."
}
cdl_component CYG_HAL_CPUTYPE {
display "cpu type"
flavor data
legal_values {"KS32C5000A" "S3C4510A"}
default_value {"S3C4510A"}
no_define
define -file system.h CYG_HAL_CPUTYPE
description "Which version of processor is on board."
}
cdl_component CYGNUM_HAL_CPUCLOCK {
display "cpu clock"
flavor data
legal_values 10000000 to 100000000
default_value 50000000
no_define
define -file system.h CYGNUM_HAL_CPUCLOCK
description "Frequency of cpu clock in Hz."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of diag/debug communication channels on the
board"
flavor data
calculated 2
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
display "Default console channel."
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
calculated 0
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "The S3C4510B TEST board has two diag/debug
serial ports. This option chooses which port will
be used to connect to a host running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
description "
The S3C4510B TEST board has two diag/debug serial ports. This
option
chooses which port will be used for diagnostic output."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
display "Console/GDB serial port baud rate"
flavor data
legal_values 9600 19200 38400 57600 115200
default_value 38400
description "
This option controls the default baud rate used for the
Console/GDB connection."
}
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants"
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated (CYGNUM_HAL_CPUCLOCK/CYGNUM_HAL_RTC_DENOMINATOR)
}
}
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "arm-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
if {1} {
default_value { (CYGHWR_THUMB && CYGHWR_HAL_ARM_BIGENDIAN)
?
"-mthumb-interwork -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -W
inline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sectio
ns -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
CYGHWR_THUMB ?
"-mthumb-interwork -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wunde
f -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti
-fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline
-Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno
-rtti -fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && !
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Wove
rloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-ex
ceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm7tdmi -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winl
ine -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections
-fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
"-mcpu=arm7tdmi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -
Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fn
o-exceptions -fvtable-gc -finit-priority" }
} else {
default_value { (CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline
-Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno
-rtti -fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && !
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Wove
rloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-ex
ceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm7tdmi -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winl
ine -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections
-fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
"-mcpu=arm7tdmi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -
Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fn
o-exceptions -fvtable-gc -finit-priority" }
}
description "
This option controls the global compiler flags which are
used to
compile all packages by default. Individual packages may
define
options which override these global flags."
}
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
if {1} {
default_value { (CYGHWR_THUMB && CYGHWR_HAL_ARM_BIGENDIAN)
?
"-mthumb-interwork -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static"
:
CYGHWR_THUMB ?
"-mthumb-interwork -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && !
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm7tdmi -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
"-mcpu=arm7tdmi -g -nostdlib -Wl,--gc-sections -Wl,-static" }
} else {
default_value { (CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && !
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm9 -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") &&
CYGHWR_HAL_ARM_BIGENDIAN ?
"-mcpu=arm7tdmi -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
"-mcpu=arm7tdmi -g -nostdlib -Wl,--gc-sections -Wl,-static" }
}
description "
This option controls the global linker flags. Individual
packages may define options which override these global
flags."
}
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the final conversion from ELF image to
binary data is handled by the platform CDL, allowing
relocation of the data if necessary."
make -priority 320 {
<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) -O binary $< $@
}
}
}
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "arm_test_ram" : \
"arm_test_rom" }
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ?
"<pkgconf/mlt_arm_test_ram.ldi>" : \
"<pkgconf/mlt_arm_test_rom.ldi>"}
}
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ?
"<pkgconf/mlt_arm_test_ram.h>" : \
"<pkgconf/mlt_arm_test_rom.h>"}
}
}
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
Enable this option if this program is to be used as a ROM
monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from
the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
cdl_component CYGPKG_CYGMON_HAL_OPTIONS {
display "CygMon HAL options"
flavor none
no_define
parent CYGPKG_CYGMON
active_if CYGPKG_CYGMON
requires CYGPKG_IO_SERIAL_ARM_TEST
requires {(CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser0\"") || \
(CYGPKG_IO_SERIAL_ARM_TEST_SERIAL0 && \
(CYGNUM_IO_SERIAL_ARM_TEST_SERIAL0_BUFSIZE == 512))}
requires {(CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser1\"") || \
(CYGPKG_IO_SERIAL_ARM_TEST_SERIAL1 && \
(CYGNUM_IO_SERIAL_ARM_TEST_SERIAL1_BUFSIZE == 512))}
description "
This option also lists the target's requirements for a valid
CygMon
configuration."
cdl_option CYGDAT_CYGMON_CONSOLE_DEV {
display "Serial port for default console"
flavor data
default_value { "\"/dev/ser0\"" }
description "
This option selects the physical device to use as the
default
console device for CygMon."
}
cdl_option CYGBLD_BUILD_CYGMON_BIN {
display "Build CygMon ROM binary image"
active_if CYGBLD_BUILD_CYGMON
default_value 1
no_define
description "This option enables the conversion of the CygMon
ELF
image to a binary image suitable for ROM
programming."
make -priority 325 {
<PREFIX>/bin/cygmon.bin : <PREFIX>/bin/cygmon.elf
$(OBJCOPY) --strip-debug --change-addresses=0xFC060000 $<
$(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot
ELF
image to a binary image suitable for ROM
programming."
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
}
****************************************************************************
*****************************
********mlt_arm_test_ram.h
****************************************************************************
*****************************
// eCos memory layout - Tue Feb 29 14:11:30 2000
// This is a generated file - do not edit
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
#define CYGMEM_REGION_ram (0x01000000)
#define CYGMEM_REGION_ram_SIZE (0x01000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x01000000 - (size_t) CYG_LABEL_NAME
(__heap1))
****************************************************************************
*****************************
********mlt_arm_test_rom.h
****************************************************************************
*****************************
// eCos memory layout - Wed Apr 11 13:49:55 2001
// This is a generated file - do not edit
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
#endif
#define CYGMEM_REGION_ram (0x01000000)
#define CYGMEM_REGION_ram_SIZE (0x01000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0)
#define CYGMEM_REGION_rom_SIZE (0x200000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x01000000 - (size_t) CYG_LABEL_NAME
(__heap1))
****************************************************************************
*****************************
**********mlt_arm_test_ram.ldi
****************************************************************************
*****************************
// eCos memory layout - Tue Feb 29 14:11:30 2000
// This is a generated file - do not edit
#include <cyg/infra/cyg_type.inc>
MEMORY
{
ram : ORIGIN = 0x01000000, LENGTH = 0x01000000
}
SECTIONS
{
SECTIONS_BEGIN
SECTION_fixed_vectors (ram, 0x01000200, LMA_EQ_VMA)
SECTION_rom_vectors (ram, 0x01020000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
****************************************************************************
*****************************
**********mlt_arm_test_rom.ldi
****************************************************************************
*****************************
// eCos memory layout - Wed Apr 11 13:49:55 2001
// This is a generated file - do not edit
#include <cyg/infra/cyg_type.inc>
MEMORY
{
ram : ORIGIN = 0x01000000, LENGTH = 0x01000000
rom : ORIGIN = 0, LENGTH = 0x200000
}
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x01000020, LMA_EQ_VMA)
SECTION_data (ram, 0x01020000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
5. I modified the redboot_RAM.ecm and redboot_ROM.ecm
************************************************************************
*******redboot_RAM.ecm*******
************************************************************************
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template
package };
cdl_savefile_command cdl_package { value_source user_value wizard_value
inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value
inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value
inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value
inferred_value };
cdl_configuration eCos {
description "" ;
hardware test ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_TEST v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
};
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 6144
};
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
user_value 1
};
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
************************************************************************
*******redboot_ROM.ecm*******
************************************************************************
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template
package };
cdl_savefile_command cdl_package { value_source user_value wizard_value
inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value
inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value
inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value
inferred_value };
cdl_configuration eCos {
description "" ;
hardware test ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_TEST v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
};
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 6144
};
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
user_value 1
};
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
After these I build the Redboot using eCos configuration tool.
Forgot to tell you that the data-bus width for the FLASH and SDRAM are all
16-bit wide. I think this is different from the SNDS board, where could I
change the data-bus width? in the hal_platform_setup.h?
How could I make the Redboot support AM29LV160 FLASH? Does it support SDRAM?
Thanks a lot!
H.Y. Roger
-----Original Message-----
From: ecos-discuss-owner@ecos.sourceware.org
[mailto:ecos-discuss-owner@ecos.sourceware.org]On Behalf Of Jonathan Larmour
Sent: Wednesday, February 11, 2004 12:45 PM
To: ying_hu@alliedtelesyn.com
Cc: ecos-discuss@sources.redhat.com
Subject: Re: [ECOS] about porting ecos in S3C4510B development board
Hu Ying wrote:
> Hi all,
>
> I just started working on porting eCos on my S3C4510B based
development
> board which uses S3C4510B, 16MByte SDRAM, 2MByte Flash (AM29LV160).
>
> I tried to build a Redboot based the SNDS100 package provided in eCos.
> But haven't succeeded :-(. I modified hal_arm_snds.cdl, the
> mlt_arm_snds_ram/rom.h/ldi, but I could see anything from the
Hyperterminal.
>
> Please drop me somp advice.
Please describe in more details the steps you took so we can tell you if
you took a wrong turning. In particular did you remember to import the .ecm
file? Since you ask:
> Do I need to include Flash driver for Redboot?
There is no flash driver for the SNDS, sorry.
> How should I set the
> serial port if I want to use the Hyperterminal with my ARM board? shall I
> choose S3C4510A or KS32C5000A?
Depends what's fitted, the closest would be S3C4510A. It's possible that
there's a difference between the A and B revisions - you'd need to see the
documentation for the chips to find out for sure. The B may just be an
errata fix version of the chip.
Jifl
--
eCosCentric http://www.eCosCentric.com/ The eCos and RedBoot experts
Visit us at Embedded World 2004, Nürnberg, Germany, 17-19 Feb, Stand 12-449
--["No sense being pessimistic, it wouldn't work anyway"]-- Opinions==mine
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and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss