Re: [ECOS] XScale PXA255 MMU Translation Table Query

["Francis Musto" <francismusto at hotmail dot com>]

On thinking about this, I think accesses to ROM & RAM will have to be 
addressed to different locations after the MMU is enabled, I cant find any 
mention of this in the examples I am using. Is this handled by ECOS in some 
hidden way? Does it copy the ROM to RAM somewhere & jump to it after the MMU 
is enabled & do RAM accesess need a different set of location defines?


> From: Andrew Lunn <andrew.lunn@ascom.ch>
> To: Francis Musto <francismusto@hotmail.com>
> CC: ecos-discuss@sources.redhat.com
> Subject: Re: [ECOS] XScale PXA255 MMU Translation Table Query
> Date: Wed, 30 Jul 2003 13:47:23 +0200
>
> On Wed, Jul 30, 2003 at 11:43:25AM +0000, Francis Musto wrote:
> > I am using the MPC5 & uE250 examples for a port to our PXA255 platform.
> >
> > I notice that both tables in hal_mmu_init map the flash from 0 to
> > 0x50000000 & SDRAM from 0xA0000000 to 0 as well as platform specific
> > peripherals to other addresses.
> >
> > Why?
> >
> > Is there a reason for not leaving everything where it's actual address 
> is?
> > If so is there some documentation discussing this?
>
> The vectors on ARM are at address 0x00-0x20. Thinks like IRQ, FIQ,
> etc. In order to change them so you can install interrupt handlers,
> they have to be in RAM, not FLASH.
>
>      Andrew

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