This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Re: [PATCH 3/9] x86: correct MPX insn w/o base or index encoding in 16-bit mode
On Wed, Mar 4, 2020 at 1:38 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16
> fails to match the templates.
>
> The SDM leaves open whether BNDC[LNU] with a GPR operand require an
> operand size override; this aspect is therefore left untouched here.
>
> gas/
> 2020-03-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (i386_addressing_mode): For 32-bit
> addressing for MPX insns without base/index.
> * testsuite/gas/i386/mpx-16bit.s,
> * testsuite/gas/i386/mpx-16bit.d: New.
> * testsuite/gas/i386/i386.exp: Run new test.
>
> opcodes/
> 2020-03-XX Jan Beulich <jbeulich@suse.com>
>
> * i386-dis.c (OP_E_memory): Exclude recording of used address
> prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
> addressed memory operands for MPX insns.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -10297,6 +10297,21 @@ i386_addressing_mode (void)
>
> if (i.prefix[ADDR_PREFIX])
> addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
> + else if (flag_code == CODE_16BIT
> + && current_templates->start->cpu_flags.bitfield.cpumpx
> + /* Avoid replacing the "16-bit addressing not allowed" diagnostic
> + from md_assemble() by "is not a valid base/index expression"
> + when there is a base and/or index. */
> + && !i.types[this_operand].bitfield.baseindex)
> + {
> + /* MPX insn memory operands with neither base nor index must be forced
> + to use 32-bit addressing in 16-bit mode. */
> + addr_mode = CODE_32BIT;
> + i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
> + ++i.prefixes;
> + gas_assert (!i.types[this_operand].bitfield.disp16);
> + gas_assert (!i.types[this_operand].bitfield.disp32);
> + }
> else
> {
Since MPX isn't available in 16-bit mode, should they be disallowed? Given that
MPX has been deprecated, I prefer an error here.
--
H.J.