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Ping: aarch64: Fix MOVPRFX markup for bf16 conversions

From: Richard Sandiford <richard dot sandiford at arm dot com>
To: binutils at sourceware dot org
Cc: nickc at redhat dot com
Date: Mon, 10 Feb 2020 11:48:54 +0000
Subject: Ping: aarch64: Fix MOVPRFX markup for bf16 conversions
References: <mpt8slnbvh9.fsf@arm.com>
Richard Sandiford <richard.sandiford@arm.com> writes:
> bfcvt converts a .S input to a .H output, so any predicated movprfx
> needs to operate on .S rather than .H.  In common with SVE2 narrowing
> top operations, bfcvtnt doesn't accept movprfx.
>
> Tested on aarch64-linux-gnu and aarch64_be-elf.  Pushed to master so far.
> Nick: ok for 2.34 too?  Would be nice to get this in if possible since
> the feature is new to 2.34.

Ping for the backport.  Obviously it's missed 2.34 at this point,
but it would be good to have it in any 2.34.1, or at least sitting
on the branch for anyone who builds directly from there.

Thanks,
Richard

>
> Thanks,
> Richard
>
>
> 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
>
> opcodes/
> 	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
> 	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
>
> gas/
> 	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
> 	.s for the movprfx.
> 	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
> 	* testsuite/gas/aarch64/sve-movprfx_28.d,
> 	* testsuite/gas/aarch64/sve-movprfx_28.l,
> 	* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
> ---
>  .../gas/aarch64/sve-bfloat-movprfx.d          |  2 +-
>  .../gas/aarch64/sve-bfloat-movprfx.s          |  2 +-
>  gas/testsuite/gas/aarch64/sve-movprfx_28.d    | 31 +++++++++++++
>  gas/testsuite/gas/aarch64/sve-movprfx_28.l    |  8 ++++
>  gas/testsuite/gas/aarch64/sve-movprfx_28.s    | 45 +++++++++++++++++++
>  opcodes/aarch64-tbl.h                         |  4 +-
>  6 files changed, 88 insertions(+), 4 deletions(-)
>  create mode 100644 gas/testsuite/gas/aarch64/sve-movprfx_28.d
>  create mode 100644 gas/testsuite/gas/aarch64/sve-movprfx_28.l
>  create mode 100644 gas/testsuite/gas/aarch64/sve-movprfx_28.s
>
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 2a99412673..2bc69a38ee 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -5107,8 +5107,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
>    BFLOAT16_SVE_INSNC ("bfdot",  0x64608000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
>    BFLOAT16_SVE_INSNC ("bfdot",  0x64604000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
>    BFLOAT16_SVE_INSNC ("bfmmla",  0x6460e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
> -  BFLOAT16_SVE_INSNC ("bfcvt",  0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
> -  BFLOAT16_SVE_INSNC ("bfcvtnt",  0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
> +  BFLOAT16_SVE_INSNC ("bfcvt",  0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
> +  BFLOAT16_SVE_INSNC ("bfcvtnt",  0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0, 0),
>    BFLOAT16_SVE_INSNC ("bfmlalt",  0x64e08400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
>    BFLOAT16_SVE_INSNC ("bfmlalb",  0x64e08000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
>    BFLOAT16_SVE_INSNC ("bfmlalt",  0x64e04400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
> diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
> index 4ba95b8950..e51bd11427 100644
> --- a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
> +++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
> @@ -23,5 +23,5 @@ Disassembly of section \.text:
>   *[0-9a-f]+:	64e34440 	bfmlalt	z0\.s, z2\.h, z3\.h\[0\]
>   *[0-9a-f]+:	0420bc20 	movprfx	z0, z1
>   *[0-9a-f]+:	658aa040 	bfcvt	z0\.h, p0/m, z2\.s
> - *[0-9a-f]+:	04512020 	movprfx	z0\.h, p0/m, z1\.h
> + *[0-9a-f]+:	04912020 	movprfx	z0\.s, p0/m, z1\.s
>   *[0-9a-f]+:	658aa040 	bfcvt	z0\.h, p0/m, z2\.s
> diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
> index c322532a80..d46da21aac 100644
> --- a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
> +++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
> @@ -27,5 +27,5 @@ movprfx z0, z1
>  bfcvt z0.h, p0/m, z2.s
>  
>  # Predicated movprfx + bfcvt
> -movprfx z0.h, p0/m, z1.h
> +movprfx z0.s, p0/m, z1.s
>  bfcvt z0.h, p0/m, z2.s
> diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.s b/gas/testsuite/gas/aarch64/sve-movprfx_28.s
> new file mode 100644
> index 0000000000..9ef0ad532f
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.s
> @@ -0,0 +1,45 @@
> +	.text
> +	.arch armv8-a+sve+bf16
> +
> +f:
> +	// OK
> +	movprfx z0.s, p1/m, z1.s
> +	bfcvt z0.h, p1/m, z2.s
> +
> +	// OK
> +	movprfx z0.s, p1/z, z1.s
> +	bfcvt z0.h, p1/m, z2.s
> +
> +	// Wrong size
> +	movprfx z0.h, p1/m, z1.h
> +	bfcvt z0.h, p1/m, z2.s
> +
> +	// Wrong size
> +	movprfx z0.h, p1/z, z1.h
> +	bfcvt z0.h, p1/m, z2.s
> +
> +	// OK
> +	movprfx z0, z1
> +	bfcvt z0.h, p1/m, z2.s
> +
> +	// Not prefixable
> +	movprfx z0, z1
> +	bfcvtnt z0.h, p1/m, z2.s
> +
> +	// Not prefixable
> +	movprfx z0.s, p1/m, z1.s
> +	bfcvtnt z0.h, p1/m, z2.s
> +
> +	// Not prefixable
> +	movprfx z0.s, p1/z, z1.s
> +	bfcvtnt z0.h, p1/m, z2.s
> +
> +	// Not prefixable
> +	movprfx z0.h, p1/m, z1.h
> +	bfcvtnt z0.h, p1/m, z2.s
> +
> +	// Not prefixable
> +	movprfx z0.h, p1/z, z1.h
> +	bfcvtnt z0.h, p1/m, z2.s
> +
> +	ret
> diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.l b/gas/testsuite/gas/aarch64/sve-movprfx_28.l
> new file mode 100644
> index 0000000000..a75289ca2a
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.l
> @@ -0,0 +1,8 @@
> +[^:]*: Assembler messages:
> +.*:15: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
> +.*:19: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
> +.*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
> +.*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
> +.*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
> +.*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
> +.*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
> diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.d b/gas/testsuite/gas/aarch64/sve-movprfx_28.d
> new file mode 100644
> index 0000000000..808d07da89
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.d
> @@ -0,0 +1,31 @@
> +#source: sve-movprfx_28.s
> +#warning_output: sve-movprfx_28.l
> +#as: -I$srcdir/$subdir --generate-missing-build-notes=no
> +#objdump: -Dr -M notes
> +
> +.* file format .*
> +
> +Disassembly of section .*:
> +
> +0+ <.*>:
> +[^:]+:	04912420 	movprfx	z0\.s, p1/m, z1\.s
> +[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s
> +[^:]+:	04902420 	movprfx	z0\.s, p1/z, z1\.s
> +[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s
> +[^:]+:	04512420 	movprfx	z0\.h, p1/m, z1\.h
> +[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s  // note: register size not compatible with previous `movprfx' at operand 1
> +[^:]+:	04502420 	movprfx	z0\.h, p1/z, z1\.h
> +[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s  // note: register size not compatible with previous `movprfx' at operand 1
> +[^:]+:	0420bc20 	movprfx	z0, z1
> +[^:]+:	658aa440 	bfcvt	z0\.h, p1/m, z2\.s
> +[^:]+:	0420bc20 	movprfx	z0, z1
> +[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
> +[^:]+:	04912420 	movprfx	z0\.s, p1/m, z1\.s
> +[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
> +[^:]+:	04902420 	movprfx	z0\.s, p1/z, z1\.s
> +[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
> +[^:]+:	04512420 	movprfx	z0\.h, p1/m, z1\.h
> +[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
> +[^:]+:	04502420 	movprfx	z0\.h, p1/z, z1\.h
> +[^:]+:	648aa440 	bfcvtnt	z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
> +[^:]+:	d65f03c0 	ret
Follow-Ups:
- Re: Ping: aarch64: Fix MOVPRFX markup for bf16 conversions
  - From: Nick Clifton
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