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[GAS][Arm] PR 25472: Enable DSP instructions with +mve
- From: "Andre Vieira (lists)" <andre dot simoesdiasvieira at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Nick Clifton <nickc at redhat dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- Date: Tue, 28 Jan 2020 14:16:16 +0000
- Subject: [GAS][Arm] PR 25472: Enable DSP instructions with +mve
Hi,
We noticed +mve was not enabling DSP instructions as it should, reported
in PR 25472.
The MVE architecture extension for Armv8.1-M Mainline implies DSP
extensions. This patch reflects that in the '+mve' command line option.
Tested on arm-vxworks, arm-wince-pe and arm-none-eabi.
Is this OK for trunk and backports to 2.33 and 2.34?
Cheers,
Andre
gas/ChangeLog:
2020-01-28 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25472
* config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding.
(armv8_1m_main_ext_table): Refactored +dsp adding and enabled
dsp for
+mve.
* testsuite/gas/arm/mve_dsp.d: New test.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 16cbac4279ef96d0edff57f83cb20935ae5196eb..9d58ebb30011825cf99ffb21a070f106cff43c70 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -31280,17 +31280,18 @@ static const struct arm_ext_table armv86a_ext_table[] =
static const struct arm_ext_table armv8m_main_ext_table[] =
{
- ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
- ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
+ ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
+ ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
};
+
static const struct arm_ext_table armv8_1m_main_ext_table[] =
{
- ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
- ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
+ ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
+ ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
ARM_EXT ("fp",
ARM_FEATURE (0, ARM_EXT2_FP16_INST,
FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
@@ -31298,10 +31299,11 @@ static const struct arm_ext_table armv8_1m_main_ext_table[] =
ARM_ADD ("fp.dp",
ARM_FEATURE (0, ARM_EXT2_FP16_INST,
FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
- ARM_EXT ("mve", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP, ARM_EXT2_MVE, 0),
ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
ARM_ADD ("mve.fp",
- ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+ ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP,
+ ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
};
diff --git a/gas/testsuite/gas/arm/mve_dsp.d b/gas/testsuite/gas/arm/mve_dsp.d
new file mode 100644
index 0000000000000000000000000000000000000000..d76c8b2c998e7a80ba19ce6f490ea1816924d868
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve_dsp.d
@@ -0,0 +1,140 @@
+# name: 32-bit Thumb DSP instructions (enabled by +mve)
+# as: -march=armv8.1-m.main+mve
+# source: arch7em.s
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> eac0 0000 pkhbt r0, r0, r0
+0[0-9a-f]+ <[^>]+> eac0 0900 pkhbt r9, r0, r0
+0[0-9a-f]+ <[^>]+> eac9 0000 pkhbt r0, r9, r0
+0[0-9a-f]+ <[^>]+> eac0 0009 pkhbt r0, r0, r9
+0[0-9a-f]+ <[^>]+> eac0 5000 pkhbt r0, r0, r0, lsl #20
+0[0-9a-f]+ <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3
+0[0-9a-f]+ <[^>]+> eac3 0102 pkhbt r1, r3, r2
+0[0-9a-f]+ <[^>]+> eac2 4163 pkhtb r1, r2, r3, asr #17
+0[0-9a-f]+ <[^>]+> fa83 f182 qadd r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa83 f192 qdadd r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa83 f1b2 qdsub r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa83 f1a2 qsub r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f103 sadd16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f103 sadd8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f103 ssub16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f103 ssub8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f123 shadd16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f123 shadd8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f123 shsub16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f123 shsub8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f143 uadd16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f143 uadd8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f143 usub16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f143 usub8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f163 uhadd16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f163 uhadd8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f163 uhsub16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f163 uhsub8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f153 uqadd16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f153 uqadd8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f153 uqsub16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f153 uqsub8 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f183 sel r1, r2, r3
+0[0-9a-f]+ <[^>]+> fb10 0000 smlabb r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0900 smlabb r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb19 0000 smlabb r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0009 smlabb r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb10 9000 smlabb r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb10 0020 smlatb r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0010 smlabt r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0030 smlatt r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 0000 smlawb r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 0010 smlawt r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 0000 smlad r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 0010 smladx r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 0000 smlsd r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 0010 smlsdx r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 0000 smmla r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 0010 smmlar r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb60 0000 smmls r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb60 0010 smmlsr r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb70 0000 usada8 r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0080 smlalbb r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 9080 smlalbb r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0980 smlalbb r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fbc9 0080 smlalbb r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fbc0 0089 smlalbb r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> fbc0 00a0 smlaltb r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0090 smlalbt r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00b0 smlaltt r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00c0 smlald r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00d0 smlaldx r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbd0 00c0 smlsld r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbd0 00d0 smlsldx r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbe0 0060 umaal r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f000 smulbb r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f900 smulbb r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb19 f000 smulbb r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb10 f009 smulbb r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb10 f020 smultb r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f010 smulbt r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f030 smultt r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 f000 smulwb r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 f010 smulwt r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 f000 smmul r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 f010 smmulr r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 f000 smuad r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 f010 smuadx r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0
+0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #10, r0
+0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #1, r9
+0[0-9a-f]+ <[^>]+> f3a0 0000 usat16 r0, #0, r0
+0[0-9a-f]+ <[^>]+> f3a0 0900 usat16 r9, #0, r0
+0[0-9a-f]+ <[^>]+> f3a0 0009 usat16 r0, #9, r0
+0[0-9a-f]+ <[^>]+> f3a9 0000 usat16 r0, #0, r9
+0[0-9a-f]+ <[^>]+> fa2f f182 sxtb16 r1, r2
+0[0-9a-f]+ <[^>]+> fa2f f889 sxtb16 r8, r9
+0[0-9a-f]+ <[^>]+> fa3f f182 uxtb16 r1, r2
+0[0-9a-f]+ <[^>]+> fa3f f889 uxtb16 r8, r9
+0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa40 f990 sxtab r9, r0, r0, ror #8
+0[0-9a-f]+ <[^>]+> fa49 f0a0 sxtab r0, r9, r0, ror #16
+0[0-9a-f]+ <[^>]+> fa40 f0b9 sxtab r0, r0, r9, ror #24
+0[0-9a-f]+ <[^>]+> fa22 f183 sxtab16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa02 f183 sxtah r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3
+