Use disassemble_info.private_data in place of insn_sets

[Alan Modra <amodra at gmail dot com>]

No cgen target uses private_data.  This patch removes a
disassemble_info field that is only used by cgen, and instead uses
private_data.  It also removes a macro that is no longer used.

include/
	* dis-asm.h (struct disassemble_info): Delete insn_sets.
	(INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define.
opcodes/
	* cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
	* disassemble.c (disassemble_init_for_target): Likewise.
	* bpf-dis.c: Regenerate.
	* epiphany-dis.c: Regenerate.
	* fr30-dis.c: Regenerate.
	* frv-dis.c: Regenerate.
	* ip2k-dis.c: Regenerate.
	* iq2000-dis.c: Regenerate.
	* lm32-dis.c: Regenerate.
	* m32c-dis.c: Regenerate.
	* m32r-dis.c: Regenerate.
	* mep-dis.c: Regenerate.
	* mt-dis.c: Regenerate.
	* or1k-dis.c: Regenerate.
	* xc16x-dis.c: Regenerate.
	* xstormy16-dis.c: Regenerate.

diff --git a/include/dis-asm.h b/include/dis-asm.h
index b4d5025811..c1746502ca 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -78,11 +78,6 @@ typedef struct disassemble_info
   enum bfd_endian endian;
   /* Endianness of code, for mixed-endian situations such as ARM BE8.  */
   enum bfd_endian endian_code;
-  /* An arch/mach-specific bitmask of selected instruction subsets, mainly
-     for processors with run-time-switchable instruction sets.  The default,
-     zero, means that there is no constraint.  CGEN-based opcodes ports
-     may use ISA_foo masks.  */
-  void *insn_sets;
 
   /* Some targets need information about the current section to accurately
      display insns.  If this is NULL, the target disassembler function
@@ -394,9 +389,6 @@ extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream,
 /* For compatibility with existing code.  */
 #define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
   init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
-#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
-  init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
-
 
 #ifdef __cplusplus
 }
diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in
index d1e06bf7b8..cf3e872de8 100644
--- a/opcodes/cgen-dis.in
+++ b/opcodes/cgen-dis.in
@@ -388,7 +388,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
     cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
   }
 #else
-  isa = info->insn_sets;
+  isa = info->private_data;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index aef2fd8644..f131ee8520 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -654,26 +654,26 @@ disassemble_init_for_target (struct disassemble_info * info)
       /* This processor in fact is little endian.  The value set here
 	 reflects the way opcodes are written in the cgen description.  */
       info->endian = BFD_ENDIAN_BIG;
-      if (! info->insn_sets)
+      if (!info->private_data)
 	{
-	  info->insn_sets = cgen_bitset_create (ISA_MAX);
+	  info->private_data = cgen_bitset_create (ISA_MAX);
 	  if (info->mach == bfd_mach_m16c)
-	    cgen_bitset_set (info->insn_sets, ISA_M16C);
+	    cgen_bitset_set (info->private_data, ISA_M16C);
 	  else
-	    cgen_bitset_set (info->insn_sets, ISA_M32C);
+	    cgen_bitset_set (info->private_data, ISA_M32C);
 	}
       break;
 #endif
 #ifdef ARCH_bpf
     case bfd_arch_bpf:
-      if (!info->insn_sets)
-        {
-          info->insn_sets = cgen_bitset_create (ISA_EBPFMAX);
-          if (info->endian == BFD_ENDIAN_BIG)
-            cgen_bitset_set (info->insn_sets, ISA_EBPFBE);
-          else
-            cgen_bitset_set (info->insn_sets, ISA_EBPFLE);
-        }
+      if (!info->private_data)
+	{
+	  info->private_data = cgen_bitset_create (ISA_EBPFMAX);
+	  if (info->endian == BFD_ENDIAN_BIG)
+	    cgen_bitset_set (info->private_data, ISA_EBPFBE);
+	  else
+	    cgen_bitset_set (info->private_data, ISA_EBPFLE);
+	}
       break;
 #endif
 #ifdef ARCH_pru

-- 
Alan Modra
Australia Development Lab, IBM