This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

RE: [PATCH] opcodes/arc: Add finer details for llock and scond

From: Claudiu Zissulescu <Claudiu dot Zissulescu at synopsys dot com>
To: Shahab Vahedi <shahab dot vahedi at gmail dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
Cc: Shahab Vahedi <Shahab dot Vahedi at synopsys dot com>, Francois Bedard <Francois dot Bedard at synopsys dot com>
Date: Wed, 4 Dec 2019 22:41:38 +0000
Subject: RE: [PATCH] opcodes/arc: Add finer details for llock and scond
Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=synopsys.com; dmarc=pass action=none header.from=synopsys.com; dkim=pass header.d=synopsys.com; arc=none
Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=812xuWNrYqlKq9I2kHXs2u+GCzS90bRUfer9t3HwUWQ=; b=AsqiFeaGEi3gNycUTPtzofl+90IqD0MoPthbgMEs/aJBBF+CZTjjNQi+ljO7YMx6BimMpCjEr7HYaQr4HFdNYDhRKJlOAzQkAQMRDHak5PGuZEfPkzDV25bgb4ShCGPIsSEWmnRPq+tm8f0OWFJkUB3YvCxs5ao+jhuUobTRslkJx1hp1eIqsVTKVzdFyKAwbWjAfjRp/y6qZA6RCWdBRw5wIF0HF9ufOvovPtQm3ikt6Ri9N9VJVh998fg97HidP31Ow6P0B2a7GAYHLkywclGn+o7O9UR0JUOsj9PxPdHJ/pQ6I4ofPvWT65GHw8wVfaCI7tVqoH7IgtxMs+tCuw==
Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jiWtJd4Dvh5o2LTtlnaeacDFGZjVxpj8avmB0uDa1cE0/tB64iF1Hg05rwg/lvMo7ShWYE10LpcShLvjVSt2kjmslWIYSIGvVM7qXekUL57pQxw7ntppKfaaaqjy/dAxKcEZZ27MeDBiaDzRthSR5u38ZV0VSc2EmhwWGg1DcbUGeX8fupVMv3+HIZxe2f5z2USNpdWZsYajG6bGOKavc8H0TjxHbDoPiN+9egrCY5D5UgOgXmO8lrcRaYQ20Hg/TeerBEWzAcKJlibStWsa//WdFFlK3Q2HWI6xInQpGnLw8vtIO8Tr8Ujmydh/mRGlaoIJyU6JC+57GHuIAf1a3Q==
References: <20191204140853.15706-1-shahab.vahedi@gmail.com>

Hi,

It looks good, I'll push it asap.

Thank you,
Claudiu

> -----Original Message-----
> From: Shahab Vahedi [mailto:shahab.vahedi@gmail.com]
> Sent: Wednesday, December 04, 2019 3:09 PM
> To: binutils@sourceware.org
> Cc: Shahab Vahedi <shahab@synopsys.com>; Claudiu Zissulescu
> <claziss@synopsys.com>; Francois Bedard <fbedard@synopsys.com>
> Subject: [PATCH] opcodes/arc: Add finer details for llock and scond
> 
> From: Shahab Vahedi <shahab@synopsys.com>
> 
> This patch changes the "class" of llock/scond from "memory"
> to "llock/scond" respectively. Moreover, it corrects the
> "data_size_mode" for llockd and scondd instructions.
> 
> These changes are necessary for GDB's atmoic sequence handler.
> 
> include/ChangeLog:
>         * opcode/arc.h (insn_class_t): Add 'LLOCK' and 'SCOND'.
> 
> opcodes/ChangeLog:
>         * arc-tbl.h (llock): Use 'LLOCK' as class.
>         (llockd): Likewise.
>         (scond): Use 'SCOND' as class.
>         (scondd): Likewise.
>         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
>         (scondd): Likewise.
> 
> Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
> ---
>  include/opcode/arc.h |  2 ++
>  opcodes/arc-tbl.h    | 42 +++++++++++++++++++++---------------------
>  2 files changed, 23 insertions(+), 21 deletions(-)
> 
> diff --git a/include/opcode/arc.h b/include/opcode/arc.h
> index d6a2b885a1a..1c027140d4e 100644
> --- a/include/opcode/arc.h
> +++ b/include/opcode/arc.h
> @@ -64,6 +64,7 @@ typedef enum
>    JUMP,
>    KERNEL,
>    LEAVE,
> +  LLOCK,
>    LOAD,
>    LOGICAL,
>    LOOP,
> @@ -76,6 +77,7 @@ typedef enum
>    PMU,
>    POP,
>    PUSH,
> +  SCOND,
>    SJLI,
>    STORE,
>    SUB,
> diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
> index 6198f91cef1..85817cbea54 100644
> --- a/opcodes/arc-tbl.h
> +++ b/opcodes/arc-tbl.h
> @@ -9214,40 +9214,40 @@
>  { "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM |
> ARC_OPCODE_ARCv2HS, LEAVE, CD1, { UIMM7_11_S }, { 0 }},
> 
>  /* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000.  */
> -{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB,
> BRAKET, RC, BRAKETdup }, { C_DI16 }},
> +{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB,
> BRAKET, RC, BRAKETdup }, { C_DI16 }},
> 
>  /* llock<.di> 0,c 0010011000101111D111CCCCCC010000.  */
> -{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA,
> BRAKET, RC, BRAKETdup }, { C_DI16 }},
> +{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA,
> BRAKET, RC, BRAKETdup }, { C_DI16 }},
> 
>  /* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000.  */
> -{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB,
> BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> +{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB,
> BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> 
>  /* llock<.di> 0,u6 0010011001101111D111uuuuuu010000.  */
> -{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA,
> BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> +{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA,
> BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> 
>  /* llock<.di> b,limm 00100bbb00101111DBBB111110010000.  */
> -{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB,
> BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> +{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { RB,
> BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> 
>  /* llock<.di> 0,limm 0010011000101111D111111110010000.  */
> -{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA,
> BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> +{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LLOCK, NONE, { ZA,
> BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> 
>  /* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010.  */
> -{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
> +{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LLOCK, NONE,
> { RB, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* llockd<.di> 0,c 0010011000101111D111CCCCCC010010.  */
> -{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
> +{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LLOCK, NONE,
> { ZA, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* llockd<.di> b,u6 00100bbb01101111DBBBuuuuuu010010.  */
> -{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> +{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LLOCK, NONE,
> { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* llockd<.di> 0,u6 0010011001101111D111uuuuuu010010.  */
> -{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> +{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LLOCK, NONE,
> { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* llockd<.di> b,limm 00100bbb00101111DBBB111110010010.  */
> -{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> +{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, LLOCK, NONE,
> { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* llockd<.di> 0,limm 0010011000101111D111111110010010.  */
> -{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> +{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, LLOCK, NONE,
> { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* lp s13 00100RRR101010000RRRssssssSSSSSS.  */
>  { "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 |
> ARC_OPCODE_ARC700, LOOP, NONE, { SIMM13_A16_20 }, { 0 }},
> @@ -15640,31 +15640,31 @@
>  { "sbcs", 0x2EE77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 |
> ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS,
> ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
> 
>  /* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001.  */
> -{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB,
> BRAKET, RC, BRAKETdup }, { C_DI16 }},
> +{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB,
> BRAKET, RC, BRAKETdup }, { C_DI16 }},
> 
>  /* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001.  */
> -{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB,
> BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> +{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB,
> BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> 
>  /* scond<.di> b,limm 00100bbb00101111DBBB111110010001.  */
> -{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB,
> BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> +{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SCOND, NONE, { RB,
> BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> 
>  /* scond<.di> limm,c 0010011000101111D111CCCCCC010001.  */
> -{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup
> }, { C_DI16 }},
> +{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM, SCOND, NONE, { LIMM, BRAKET, RC, BRAKETdup },
> { C_DI16 }},
> 
>  /* scond<.di> limm,u6 0010011001101111D111uuuuuu010001.  */
> -{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20,
> BRAKETdup }, { C_DI16 }},
> +{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM, SCOND, NONE, { LIMM, BRAKET, UIMM6_20,
> BRAKETdup }, { C_DI16 }},
> 
>  /* scond<.di> limm,limm 0010011000101111D111111110010001.  */
> -{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, LIMMdup,
> BRAKETdup }, { C_DI16 }},
> +{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 |
> ARC_OPCODE_ARCv2EM, SCOND, NONE, { LIMM, BRAKET, LIMMdup,
> BRAKETdup }, { C_DI16 }},
> 
>  /* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011.  */
> -{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
> +{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, SCOND,
> NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011.  */
> -{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
> +{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, SCOND,
> NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* scondd<.di> b,limm 00100bbb00101111DBBB111110010011.  */
> -{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY,
> NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
> +{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, SCOND,
> NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
> 
>  /* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA.  */
>  { "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM |
> ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
> --
> 2.24.0

References:
- [PATCH] opcodes/arc: Add finer details for llock and scond
  - From: Shahab Vahedi

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]