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Re: [PATCH] Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register
- From: Nick Clifton <nickc at redhat dot com>
- To: Jan Beulich <jbeulich at suse dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Richard Earnshaw <rearnsha at arm dot com>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Date: Mon, 11 Nov 2019 11:45:40 +0000
- Subject: Re: [PATCH] Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register
- References: <275d8dc8-b87b-c737-ab5b-314a2f20b4ac@suse.com>
Hi Jan,
> gas/
> 2019-11-11 Jan Beulich <jbeulich@suse.com>
>
> * testsuite/gas/aarch64/illegal-sve2.s: Add smaxp/sminp cases
> with mismatched 1st and 3rd operands.
> * testsuite/gas/aarch64/illegal-sve2.l: Adjust expectations.
>
> opcodes/
> 2019-11-11 Jan Beulich <jbeulich@suse.com>
>
> * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
> smaxp/sminp entries' "tied_operand" field to 2.
Approved - please apply.
Cheers
Nick