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[PATCH 5/5] x86: support further AMD Zen2 instructions
- From: Jan Beulich <jbeulich at suse dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Mon, 4 Nov 2019 16:06:53 +0100
- Subject: [PATCH 5/5] x86: support further AMD Zen2 instructions
- References: <93fcaa53-113b-d240-4c34-7dd4944cbe98@suse.com>
Both RDPRU and MCOMMIT have been publicly documented meanwhile:
https://www.amd.com/system/files/TechDocs/24594.pdf.
gas/
2019-11-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_arch): Add .rdpru and .mcommit entries.
* doc/c-i386.texi: Mention rdpru and mcommit.
* testsuite/gas/i386/arch-13.s,
testsuite/gas/i386/x86-64-arch-3.s: Add mcommit and rdpru cases.
* testsuite/gas/i386/arch-13.d,
testsuite/gas/i386/x86-64-arch-3.d: Extend -march=. Adjust
expectations.
* testsuite/gas/i386/arch-13-znver1.d,
testsuite/gas/i386/x86-64-arch-3-znver1.d: Extend -march=.
opcodes/
2019-11-XX Jan Beulich <jbeulich@suse.com>
* i386-dis.c (prefix_table): Add mcommit.
(rm_table): Add rdpru.
* i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
(cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
* i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
(union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
* i386-opc.tbl (mcommit, rdpru): New.
* i386-init.h, i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1092,6 +1092,10 @@ static const arch_entry cpu_arch[] =
CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
{ STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
CPU_ENQCMD_FLAGS, 0 },
+ { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN,
+ CPU_RDPRU_FLAGS, 0 },
+ { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN,
+ CPU_MCOMMIT_FLAGS, 0 },
};
static const noarch_entry cpu_noarch[] =
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -245,6 +245,8 @@ accept various extension mnemonics. For
@code{pconfig},
@code{waitpkg},
@code{cldemote},
+@code{rdpru},
+@code{mcommit},
@code{lwp},
@code{fma4},
@code{xop},
@@ -1366,7 +1368,8 @@ supported on the CPU specified. The cho
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
-@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
+@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
+@item @samp{.mcommit}
@end multitable
Apart from the warning, there are only two other effects on
--- a/gas/testsuite/gas/i386/arch-13-znver1.d
+++ b/gas/testsuite/gas/i386/arch-13-znver1.d
@@ -1,5 +1,5 @@
#source: arch-13.s
-#as: -march=znver1+rdpid+clwb+wbnoinvd
+#as: -march=znver1+rdpid+clwb+wbnoinvd+rdpru+mcommit
#objdump: -dw
#name: i386 arch 13 (znver1)
#dump: arch-13.d
--- a/gas/testsuite/gas/i386/arch-13.d
+++ b/gas/testsuite/gas/i386/arch-13.d
@@ -1,4 +1,4 @@
-#as: -march=i686+smap+adx+rdseed+clzero+xsavec+xsaves+clflushopt+mwaitx+rdpid+clwb+wbnoinvd
+#as: -march=i686+smap+adx+rdseed+clzero+xsavec+xsaves+clflushopt+mwaitx+rdpid+clwb+wbnoinvd+rdpru+mcommit
#objdump: -dw
#name: i386 arch 13
@@ -25,6 +25,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 fb mwaitx %eax,%ecx,%ebx
[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb \(%ecx\)
[ ]*[a-f0-9]+:[ ]*66 0f ae b4 f4 c0 1d fe ff[ ]*clwb -0x1e240\(%esp,%esi,8\)
+[ ]*[a-f0-9]+:[ ]*f3 0f 01 fa[ ]*mcommit[ ]*
[ ]*[a-f0-9]+:[ ]*f3 0f c7 f8[ ]*rdpid %eax
+[ ]*[a-f0-9]+:[ ]*0f 01 fd[ ]*rdpru[ ]*
[ ]*[a-f0-9]+:[ ]*f3 0f 09[ ]*wbnoinvd[ ]*
#pass
--- a/gas/testsuite/gas/i386/arch-13.s
+++ b/gas/testsuite/gas/i386/arch-13.s
@@ -29,8 +29,14 @@
clwb (%ecx) # CLWB
clwb -123456(%esp,%esi,8) # CLWB
+# mcommit instruction
+ mcommit
+
# rdpid instruction
rdpid %eax
+# rdpru instruction
+ rdpru
+
# wbnoinvd instruction
wbnoinvd
--- a/gas/testsuite/gas/i386/x86-64-arch-3-znver1.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-3-znver1.d
@@ -1,5 +1,5 @@
#source: x86-64-arch-3.s
-#as: -march=znver1+rdpid+clwb+wbnoinvd
+#as: -march=znver1+rdpid+clwb+wbnoinvd+rdpru+mcommit
#objdump: -dw
#name: x86-64 arch 3 (znver1)
#dump: x86-64-arch-3.d
--- a/gas/testsuite/gas/i386/x86-64-arch-3.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-3.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+smap+adx+rdseed+clzero+sha+xsavec+xsaves+clflushopt+mwaitx+rdpid+clwb+wbnoinvd
+#as: -march=generic64+smap+adx+rdseed+clzero+sha+xsavec+xsaves+clflushopt+mwaitx+rdpid+clwb+wbnoinvd+rdpru+mcommit
#objdump: -dw
#name: x86-64 arch 3
@@ -29,7 +29,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 fb mwaitx %eax,%ecx,%ebx
[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb \(%rcx\)
[ ]*[a-f0-9]+:[ ]*66 42 0f ae b4 f0 23 01 00 00[ ]*clwb 0x123\(%rax,%r14,8\)
+[ ]*[a-f0-9]+:[ ]*f3 0f 01 fa[ ]*mcommit[ ]*
[ ]*[a-f0-9]+:[ ]*f3 0f c7 f8[ ]*rdpid %rax
[ ]*[a-f0-9]+:[ ]*f3 41 0f c7 fa[ ]*rdpid %r10
+[ ]*[a-f0-9]+:[ ]*0f 01 fd[ ]*rdpru[ ]*
[ ]*[a-f0-9]+:[ ]*f3 0f 09[ ]*wbnoinvd[ ]*
#pass
--- a/gas/testsuite/gas/i386/x86-64-arch-3.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-3.s
@@ -32,9 +32,15 @@
clwb (%rcx) # CLWB
clwb 0x123(%rax,%r14,8) # CLWB
+# mcommit instruction
+ mcommit
+
# rdpid instruction
rdpid %rax
rdpid %r10
+# rdpru instruction
+ rdpru
+
# wbnoinvd instruction
wbnoinvd
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3647,6 +3647,7 @@ static const struct dis386 prefix_table[
/* PREFIX_0F01_REG_7_MOD_3_RM_2 */
{
{ "monitorx", { { OP_Monitor, 0 } }, 0 },
+ { "mcommit", { Skip_MODRM }, 0 },
},
/* PREFIX_0F01_REG_7_MOD_3_RM_3 */
@@ -11030,6 +11031,7 @@ static const struct dis386 rm_table[][8]
{ PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
{ PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
{ "clzero", { Skip_MODRM }, 0 },
+ { "rdpru", { Skip_MODRM }, 0 },
},
{
/* RM_0F1E_P_1_MOD_3_REG_7 */
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -102,7 +102,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ZNVER1_FLAGS",
"CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_AVX2_FLAGS|CpuSSE4A|CpuABM|CpuSVME|CpuAES|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" },
{ "CPU_ZNVER2_FLAGS",
- "CPU_ZNVER1_FLAGS|CpuRDPID|CpuWBNOINVD|CpuCLWB" },
+ "CPU_ZNVER1_FLAGS|CpuCLWB|CpuRDPID|CpuRDPRU|CpuMCOMMIT|CpuWBNOINVD" },
{ "CPU_BTVER1_FLAGS",
"CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuABM|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME|CpuLZCNT" },
{ "CPU_BTVER2_FLAGS",
@@ -303,6 +303,10 @@ static initializer cpu_flag_init[] =
"CpuENQCMD" },
{ "CPU_AVX512_VP2INTERSECT_FLAGS",
"CpuAVX512_VP2INTERSECT" },
+ { "CPU_RDPRU_FLAGS",
+ "CpuRDPRU" },
+ { "CPU_MCOMMIT_FLAGS",
+ "CpuMCOMMIT" },
{ "CPU_ANY_X87_FLAGS",
"CPU_ANY_287_FLAGS|Cpu8087" },
{ "CPU_ANY_287_FLAGS",
@@ -596,6 +600,8 @@ static bitfield cpu_flags[] =
BITFIELD (CpuMOVDIRI),
BITFIELD (CpuMOVDIR64B),
BITFIELD (CpuENQCMD),
+ BITFIELD (CpuRDPRU),
+ BITFIELD (CpuMCOMMIT),
#ifdef CpuUnused
BITFIELD (CpuUnused),
#endif
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -243,6 +243,10 @@ enum
CpuMOVDIR64B,
/* ENQCMD instruction required */
CpuENQCMD,
+ /* RDPRU instruction required */
+ CpuRDPRU,
+ /* MCOMMIT instruction required */
+ CpuMCOMMIT,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
@@ -372,6 +376,8 @@ typedef union i386_cpu_flags
unsigned int cpumovdiri:1;
unsigned int cpumovdir64b:1;
unsigned int cpuenqcmd:1;
+ unsigned int cpurdpru:1;
+ unsigned int cpumcommit:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4794,3 +4794,15 @@ vp2intersectd, 3, 0xf268, None, 1, CpuAV
vp2intersectq, 3, 0xf268, None, 1, CpuAVX512_VP2INTERSECT, Modrm|VexOpcode|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
// VP2INTERSECT instructions end.
+
+// MCOMMIT instruction
+
+mcommit, 0, 0xf30f01fa, None, 3, CpuMCOMMIT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// MCOMMIT instruction end
+
+// RDPRU instruction
+
+rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// RDPRU instruction end