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Re: [PATCH v2 5/9] x86: improve handling of insns with ambiguous operand sizes

From: "H.J. Lu" <hjl dot tools at gmail dot com>
To: Jan Beulich <jbeulich at suse dot com>
Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>
Date: Thu, 31 Oct 2019 10:26:32 -0700
Subject: Re: [PATCH v2 5/9] x86: improve handling of insns with ambiguous operand sizes
References: <b53b0a7a-781c-e705-82a1-3680bf635cbc@suse.com> <9c1f52a7-1805-a6b7-6951-9440de7e1d8d@suse.com> <CAMe9rOpW93TJ2cPpXk2k8D1d8JpsWUm0vkFZbYd+7_e=RV19Vw@mail.gmail.com> <41785a90-2392-f07c-fee4-3950b712ed7c@suse.com> <CAMe9rOqEANPThcWKcEuwqS-ZJW=T5mEZ4WxB7YTAfYtKWhEFWg@mail.gmail.com> <3ea4c27c-33af-d9b3-b5d3-8fa1e0bf7459@suse.com>

On Thu, Oct 31, 2019 at 2:24 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 31.10.2019 00:57, H.J. Lu wrote:
> > On Wed, Oct 30, 2019 at 12:59 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 29.10.2019 18:55,  H.J. Lu  wrote:
> >>> On Mon, Oct 28, 2019 at 1:05 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>
> >>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to
> >>>> 8-bit operand size") pointed out a very bad case, but the underlying
> >>>> problem is, as mentioned on various occasions, much larger: Silently
> >>>> selecting a (nowhere documented afaict) certain default operand size
> >>>> when there's no "sizing" suffix and no suitable register operand(s) is
> >>>> simply dangerous (for the programmer to make mistakes).
> >>>>
> >>>> While in Intel syntax mode such mistakes already lead to an error (which
> >>>> is going to remain that way), AT&T syntax mode now gains warnings in
> >>>> such cases by default, which can be suppressed or promoted to an error
> >>>> if so desired by the programmer. Furthermore at least general purpose
> >>>> insns now consistently have a default applied (alongside the warning
> >>>> emission), rather than accepting some and refusing others.
> >>>>
> >>>> No warnings are (as before) to be generated for "DefaultSize" insns as
> >>>> well as ones acting on selector and other fixed-width values. The set of
> >>>> "DefaultSize" ones gets slightly widened for the purposes here.
> >>>
> >>> What is the advantage to add DefaultSize vs the alternative?
> >>
> >> I don't know what alternative you refer to; if you mean some
> >> hypothetical one, then the advantage of simply adding
> >> DefaultSize as done here is likely that it allows to not add or
> >> further complicate logic in tc-i386*.c. Furthermore the ones which
> >> get the attribute added should have had it already before, if the
> >> comment "default insn size depends on mode" is to be trusted.
> >>
> >
> > DefaultSize is added to some instructions and then they are excluded:
> >
> > +          /* exclude jmp/ljmp */
> > +          && strcmp (i.tm.name, "jmp") && strcmp (i.tm.name, "ljmp")
> > +          /* exclude byte-displacement jumps */
> > +          && !i.tm.opcode_modifier.jumpbyte
> > +          /* exclude lgdt/lidt/sgdt/sidt */
> > +          && (i.tm.base_opcode != 0x0f01 || i.tm.extension_opcode > 3)
> >            /* exclude fldenv/frstor/fsave/fstenv */
> >            && i.tm.opcode_modifier.no_ssuf)
> >
> > It looks odd.
>
> But this isn't the only place where defaultsize gets evaluated.
> See how lgdt/lidt/sgdt/sidt already have the attribute in the
> opcode table, but need exclusion here now too. The alternative
> would be two independent attributes - one to be evaluated here,
> and the other to be evaluated further down in the function. Yet
> again - this dual use has been there before, and just needs
> suitable extending of the logic now.
>

Normally instructions with DefaultSize have i.suffix unset.  Except with
.code16gcc, which is used to support 16-bit mode with 32-bit address,
i.suffix is set to 'l' for 32-bit address.   However,
iret/fldenv/frstor/fsave/fstenv
are exceptions since they need 16-bit variants.  So we need 2 different
DefaultSize behaviors for .code16gcc, one uses LONG_MNEM_SUFFIX
and the other uses WORD_MNEM_SUFFIX.  We should update
DefaultSize to properly encode iret/fldenv/frstor/fsave/fstenv for
.code16gcc, instead of checking i.tm.opcode_modifier.no_ssuf.
Something like this.

-- 
H.J.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index f26b17c956..485ad87662 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6335,12 +6335,10 @@ process_suffix (void)
 	abort ();
     }
   else if (i.tm.opcode_modifier.defaultsize
-	   && !i.suffix
-	   /* exclude fldenv/frstor/fsave/fstenv */
-	   && i.tm.opcode_modifier.no_ssuf)
+	   && !i.suffix)
     {
       if (stackop_size == LONG_MNEM_SUFFIX
-	  && i.tm.base_opcode == 0xcf)
+	  && i.tm.opcode_modifier.defaultsize == DEFAULTSIZE16BIT)
 	{
 	  /* stackop_size is set to LONG_MNEM_SUFFIX for the
 	     .code16gcc directive to support 16-bit mode with
@@ -6348,7 +6346,8 @@ process_suffix (void)
 	     16-bit IRET (opcode 0xcf) to return from an interrupt
 	     handler.  */
 	  i.suffix = WORD_MNEM_SUFFIX;
-	  as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
+	  if (i.tm.base_opcode == 0xcf)
+	    as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
 	}
       else
 	i.suffix = stackop_size;
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 8727f11848..83ac3cf692 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -421,7 +421,9 @@ enum
   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
   IgnoreSize,
-  /* default insn size depends on mode */
+  /* default insn size depends on address mode */
+#define DEFAULTSIZEADDRESS	1
+#define DEFAULTSIZE16BIT	2
   DefaultSize,
   /* b suffix on instruction illegal */
   No_bSuf,
@@ -647,7 +649,7 @@ typedef struct i386_opcode_modifier
   unsigned int size:2;
   unsigned int checkregsize:1;
   unsigned int ignoresize:1;
-  unsigned int defaultsize:1;
+  unsigned int defaultsize:2;
   unsigned int no_bsuf:1;
   unsigned int no_wsuf:1;
   unsigned int no_lsuf:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 02c83a30f8..55aad324d3 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -38,6 +38,9 @@
 #define Size32 Size=SIZE32
 #define Size64 Size=SIZE64
 
+#define DefaultSizeAddress DefaultSize=DEFAULTSIZEADDRESS
+#define DefaultSize16Bit   DefaultSize=DEFAULTSIZE16BIT
+
 // RegMem implies a ModR/M byte
 #define RegMem Modrm|RegMem
 
@@ -124,30 +127,30 @@ movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
 movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 }
 
 // Push instructions.
-push, 1, 0x50, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
-push, 1, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
-push, 1, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S }
-push, 1, 0x68, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 }
-push, 1, 0x6, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
+push, 1, 0x50, None, 1, CpuNo64, ShortForm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
+push, 1, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
+push, 1, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S }
+push, 1, 0x68, None, 1, Cpu186|CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 }
+push, 1, 0x6, None, 1, CpuNo64, ShortForm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
 // In 64bit mode, the operand size is implicitly 64bit.
-push, 1, 0x50, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
-push, 1, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
-push, 1, 0x6a, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S }
-push, 1, 0x68, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S }
-push, 1, 0xfa0, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
+push, 1, 0x50, None, 1, Cpu64, ShortForm|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
+push, 1, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
+push, 1, 0x6a, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S }
+push, 1, 0x68, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S }
+push, 1, 0xfa0, None, 2, Cpu64, ShortForm|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
 
-pusha, 0, 0x60, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+pusha, 0, 0x60, None, 1, Cpu186|CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // Pop instructions.
-pop, 1, 0x58, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
-pop, 1, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
-pop, 1, 0x7, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
+pop, 1, 0x58, None, 1, CpuNo64, ShortForm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
+pop, 1, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
+pop, 1, 0x7, None, 1, CpuNo64, ShortForm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
 // In 64bit mode, the operand size is implicitly 64bit.
-pop, 1, 0x58, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
-pop, 1, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
-pop, 1, 0xfa1, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
+pop, 1, 0x58, None, 1, Cpu64, ShortForm|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
+pop, 1, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
+pop, 1, 0xfa1, None, 2, Cpu64, ShortForm|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
 
-popa, 0, 0x61, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+popa, 0, 0x61, None, 1, Cpu186|CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // Exchange instructions.
 // xchg commutes:  we allow both operand orders.
@@ -186,10 +189,10 @@ clts, 0, 0xf06, None, 2, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu
 cmc, 0, 0xf5, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 lahf, 0, 0x9f, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 sahf, 0, 0x9e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-pushf, 0, 0x9c, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-pushf, 0, 0x9c, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
-popf, 0, 0x9d, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-popf, 0, 0x9d, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
+pushf, 0, 0x9c, None, 1, CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+pushf, 0, 0x9c, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
+popf, 0, 0x9d, None, 1, CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+popf, 0, 0x9d, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
 stc, 0, 0xf9, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 std, 0, 0xfd, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 sti, 0, 0xfb, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@@ -346,18 +349,18 @@ shrd, 3, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {
 shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 
 // Control transfer instructions.
-call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 }
-call, 1, 0xe8, None, 1, Cpu64, AMD64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
-call, 1, 0xe8, None, 1, Cpu64, Intel64|JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
-call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|JumpAbsolute }
-call, 1, 0xff, 0x2, 1, Cpu64, AMD64|Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|JumpAbsolute }
-call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|JumpAbsolute }
+call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 }
+call, 1, 0xe8, None, 1, Cpu64, AMD64|JumpDword|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
+call, 1, 0xe8, None, 1, Cpu64, Intel64|JumpDword|DefaultSizeAddress|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
+call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|JumpAbsolute }
+call, 1, 0xff, 0x2, 1, Cpu64, AMD64|Modrm|DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|JumpAbsolute }
+call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|DefaultSizeAddress|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|JumpAbsolute }
 // Intel Syntax
-call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
+call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
 // Intel Syntax
-call, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|JumpAbsolute }
-lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
-lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|JumpAbsolute }
+call, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSizeAddress|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|JumpAbsolute }
+lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
+lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|JumpAbsolute }
 
 jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
 jmp, 1, 0xeb, None, 1, Cpu64, AMD64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S }
@@ -372,20 +375,20 @@ jmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|
 ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
 ljmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|JumpAbsolute }
 
-ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 }
-ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0, 0xc3, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
-ret, 1, 0xc2, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
-lret, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
-lret, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
+ret, 0, 0xc3, None, 1, CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 }
+ret, 1, 0xc2, None, 1, CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0, 0xc3, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
+ret, 1, 0xc2, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+lret, 0, 0xcb, None, 1, 0, DefaultSizeAddress|No_bSuf|No_sSuf|No_ldSuf, { 0 }
+lret, 1, 0xca, None, 1, 0, DefaultSizeAddress|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
 // Intel Syntax.
-retf, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
-retf, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
+retf, 0, 0xcb, None, 1, 0, DefaultSizeAddress|No_bSuf|No_sSuf|No_ldSuf, { 0 }
+retf, 1, 0xca, None, 1, 0, DefaultSizeAddress|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
 
-enter, 2, 0xc8, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm8 }
-enter, 2, 0xc8, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16, Imm8 }
-leave, 0, 0xc9, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-leave, 0, 0xc9, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
+enter, 2, 0xc8, None, 1, Cpu186|CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm8 }
+enter, 2, 0xc8, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16, Imm8 }
+leave, 0, 0xc9, None, 1, Cpu186|CpuNo64, DefaultSizeAddress|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+leave, 0, 0xc9, None, 1, Cpu64, DefaultSizeAddress|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
 
 // Conditional jumps.
 jo, 1, 0x70, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
@@ -523,7 +526,7 @@ bts, 2, 0xfba, 0x5, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPref
 int, 1, 0xcd, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
 int3, 0, 0xcc, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 into, 0, 0xce, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-iret, 0, 0xcf, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
+iret, 0, 0xcf, None, 1, 0, DefaultSize16Bit|No_bSuf|No_sSuf|No_ldSuf, { 0 }
 // i386sl, i486sl, later 486, and Pentium.
 rsm, 0, 0xfaa, None, 2, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
@@ -770,12 +773,12 @@ fstsw, 0, 0xdfe0, None, 2, Cpu287|Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu
 fnclex, 0, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 fclex, 0, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 }
 // Short forms of fldenv, fstenv use data size prefix.
-fnstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
-fstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
-fldenv, 1, 0xd9, 0x4, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
-fnsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
-fsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
-frstor, 1, 0xdd, 0x4, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+fnstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize16Bit|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+fstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize16Bit|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
+fldenv, 1, 0xd9, 0x4, 1, CpuFP, Modrm|DefaultSize16Bit|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+fnsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize16Bit|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+fsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize16Bit|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
+frstor, 1, 0xdd, 0x4, 1, CpuFP, Modrm|DefaultSize16Bit|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
 // 8087 only
 fneni, 0, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 feni, 0, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 }
@@ -2525,7 +2528,7 @@ xrelease, 0, 0xf3, None, 1, CpuHLE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l
 
 // RTM instructions
 xabort, 1, 0xc6f8, None, 2, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
-xbegin, 1, 0xc7f8, None, 2, CpuRTM,  JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
+xbegin, 1, 0xc7f8, None, 2, CpuRTM,  JumpDword|DefaultSizeAddress|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
 xend, 0, 0xf01d5, None, 3, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 xtest, 0, 0xf01d6, None, 3, CpuHLE|CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
@@ -2787,8 +2790,8 @@ pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N
 // AMD extensions.
 syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
-sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
+sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSizeAddress|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
+sysret, 0, 0xf07, None, 2, Cpu64, DefaultSizeAddress|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
 swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

Follow-Ups:
- [PATCH] i386: Add .code16gcc fldenv tests
  - From: H.J. Lu

References:
- [PATCH v2 0/9] x86: operand size handling improvements
  - From: Jan Beulich
- [PATCH v2 5/9] x86: improve handling of insns with ambiguous operand sizes
  - From: Jan Beulich
- Re: [PATCH v2 5/9] x86: improve handling of insns with ambiguous operand sizes
  - From: H.J. Lu
- Re: [PATCH v2 5/9] x86: improve handling of insns with ambiguous operand sizes
  - From: Jan Beulich
- Re: [PATCH v2 5/9] x86: improve handling of insns with ambiguous operand sizes
  - From: H.J. Lu
- Re: [PATCH v2 5/9] x86: improve handling of insns with ambiguous operand sizes
  - From: Jan Beulich

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