[Patch][gas][aarch64] Implement the Armv8.6-A Data Gathering Hint mnemonic [10/10]

[Mihail Ionescu <mihail dot ionescu at foss dot arm dot com>]

Hi,

This patch is part of a series that adds support for Armv8.6-A
to binutils.

In this last patch, the new Data Gathering Hint mnemonic is introduced.


gas/ChangeLog:

2019-09-13  Mihail Ionescu  <mihail.ionescu@arm.com>

	* testsuite/gas/aarch64/dgh.s: New test.
	* testsuite/gas/aarch64/dgh.d: New test.

opcodes/ChangeLog:

2019-09-13  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
	(aarch64_opcode_table): Add data gathering hint mnemonic.
	* opcodes/aarch64-dis-2.c: Account for new instruction.


Regression tested on arm-none-eabi.
Is it ok for trunk?

Regards,
Mihail


###############     Attachment also inlined for ease of reply    ###############
                Inline version does not contain generated files


diff --git a/gas/testsuite/gas/aarch64/dgh.d b/gas/testsuite/gas/aarch64/dgh.d
new file mode 100644
index 0000000000000000000000000000000000000000..6e196015a6f0acb470a137fb971c931ce3f445bf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dgh.d
@@ -0,0 +1,11 @@
+#name: V8.6 Data Gathering Hint
+#as: -march=armv8.6-a
+#objdump: -dr
+
+.* file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <\.text>:
+ *[0-9a-f]*:	d50320df 	hint	#0x6
+ *[0-9a-f]*:	d50320df 	hint	#0x6
diff --git a/gas/testsuite/gas/aarch64/dgh.s b/gas/testsuite/gas/aarch64/dgh.s
new file mode 100644
index 0000000000000000000000000000000000000000..6470cd0937caf16a9b28ca5112a56ce68ac4e372
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dgh.s
@@ -0,0 +1,4 @@
+# Test for the V8.6-a Data Gathering Hint instruction
+
+dgh
+hint #6
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5305c0c63cdacb91dce1bb4b7af7cf07fff587f7..f890032f266e058e3b2882b16fe2f8cf39a47c57 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2557,6 +2557,8 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
 #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
+#define V8_6_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_6, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
@@ -5072,6 +5074,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
   V8_4_INSN ("stlur",    0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
   V8_4_INSN ("ldapur",   0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
 
+  /* V8.6 instructions */
+  V8_6_INSN("dgh",  0xd50320df, 0xffffffff, aarch64_misc, OP0 (), {}, 0),
+
   /* Matrix Multiply instructions.  */
   INT8MATMUL_SVE_INSNC ("smmla",  0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
   INT8MATMUL_SVE_INSNC ("ummla",  0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),

Attachment: diff09.patch
Description: Text document