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The generated files in this patch were too large to send inline, I hope it is acceptable to send this as a gzipped .patch file instead. This adds a riscv port of the simulator, based on the cgen based cpu description. On Wed, 11 Sep 2019 at 17:50, Edward Jones <ed.jones@embecosm.com> wrote: > > We're looking to add a cpu description for the riscv architecture > plus a simulator port. The simulator has support for rv{32,64}imacfd > and is capable of running small programs compiled against newlib. > > The first patch contains binutils changes, and the second > patch contains the simulator. > > The cpu description adds generic cgen dependencies to libopcodes, > plus the generated riscv files. These sit along side the existing > riscv files in opcodes/ which are used by binutils and the > assembler. > > This work was done on behalf of Embecosm with contributions > from Mary Bennett, Ed Jones, Craig Blackmore, Andrew Burgess > and Mark Corbin. > > Testing > ------- > The changes include a testsuite with a little over 100 simple > tests for a decent subset of the risc-v instructions. More > substantial tests are being added. > > A subset of the GCC testsuite (c-torture compile+execute) is > being used to test this nightly with the following latest > results: > > === gcc Summary === > > # of expected passes 60739 > # of unexpected failures 84 > # of unexpected successes 2 > # of expected failures 228 > # of unresolved testcases 95 > # of unsupported tests 800 > > (Upstream GNU RV32 tool chain using Newlib and CGEN-based sim) > > Known Limitations > ----------------- > There are a number of known limitations which we're working > on. In rough order of priority: > > 1) TLS is currently non-functional (the thread pointer is > not initialized at startup). This is one of the causes > of GCC regression failures. > 2) Floating point rounding modes not selectable. Currently > this is fixed to round-to-nearest. > 3) Only the user-mode ISA is supported plus a handful of > CSRs. A small number of system calls are emulated (those > used by the riscv port of newlib) > 4) No support for the standard 'Q' extension > > Regards, > Ed > > > Edward Jones (2): > RISC-V: Add cgen cpu description and generated files > RISC-V: Add cgen-based simulator port > > cpu/ChangeLog | 5 + > cpu/riscv.cpu | 3688 +++ > cpu/riscv.opc | 1052 + > gdb/ChangeLog | 3 + > gdb/configure.tgt | 1 + > include/gdb/ChangeLog | 4 + > include/gdb/sim-riscv.h | 54 + > opcodes/ChangeLog | 22 + > opcodes/Makefile.am | 13 +- > opcodes/Makefile.in | 18 +- > opcodes/configure | 2 +- > opcodes/configure.ac | 2 +- > opcodes/disassemble.c | 2 +- > opcodes/disassemble.h | 2 +- > opcodes/riscv-cgen-asm.c | 1437 ++ > opcodes/riscv-cgen-desc.c | 3537 +++ > opcodes/riscv-cgen-desc.h | 298 + > opcodes/riscv-cgen-dis.c | 937 + > opcodes/riscv-cgen-ibld.c | 2540 ++ > opcodes/riscv-cgen-opc.c | 6133 +++++ > opcodes/riscv-cgen-opc.h | 251 + > opcodes/riscv-dis.c | 2 +- > sim/ChangeLog | 36 + > sim/common/ChangeLog | 7 + > sim/common/cgen-accfp.c | 24 + > sim/common/cgen-mem.h | 6 +- > sim/configure | 8 + > sim/configure.tgt | 3 + > sim/riscv/Makefile.in | 179 + > sim/riscv/aclocal.m4 | 119 + > sim/riscv/arch.h | 30 + > sim/riscv/arch32.c | 53 + > sim/riscv/arch32.h | 53 + > sim/riscv/arch64.c | 53 + > sim/riscv/arch64.h | 53 + > sim/riscv/config.in | 248 + > sim/riscv/configure | 15961 +++++++++++++ > sim/riscv/configure.ac | 23 + > sim/riscv/cpu32.c | 261 + > sim/riscv/cpu32.h | 1307 + > sim/riscv/cpu64.c | 261 + > sim/riscv/cpu64.h | 1346 ++ > sim/riscv/cpuall.h | 30 + > sim/riscv/cpuall32.h | 71 + > sim/riscv/cpuall64.h | 71 + > sim/riscv/decode32.c | 4985 ++++ > sim/riscv/decode32.h | 135 + > sim/riscv/decode64.c | 5122 ++++ > sim/riscv/decode64.h | 157 + > sim/riscv/mloop.in | 108 + > sim/riscv/model32.c | 27429 +++++++++++++++++++++ > sim/riscv/model64.c | 36949 +++++++++++++++++++++++++++++ > sim/riscv/riscv-sim.h | 47 + > sim/riscv/riscv.c | 298 + > sim/riscv/sem32.c | 6046 +++++ > sim/riscv/sem64.c | 8309 +++++++ > sim/riscv/sim-if.c | 169 + > sim/riscv/sim-main.h | 90 + > sim/riscv/traps.c | 165 + > sim/testsuite/ChangeLog | 5 + > sim/testsuite/configure | 3 + > sim/testsuite/sim/riscv/ChangeLog | 137 + > sim/testsuite/sim/riscv/add.S | 16 + > sim/testsuite/sim/riscv/addi.S | 15 + > sim/testsuite/sim/riscv/alltests.exp | 34 + > sim/testsuite/sim/riscv/amoaddw.S | 34 + > sim/testsuite/sim/riscv/amoandw.S | 24 + > sim/testsuite/sim/riscv/amomaxuw.S | 49 + > sim/testsuite/sim/riscv/amomaxw.S | 49 + > sim/testsuite/sim/riscv/amominuw.S | 49 + > sim/testsuite/sim/riscv/amominw.S | 49 + > sim/testsuite/sim/riscv/amoorw.S | 24 + > sim/testsuite/sim/riscv/amoswapw.S | 34 + > sim/testsuite/sim/riscv/amoxorw.S | 24 + > sim/testsuite/sim/riscv/and.S | 16 + > sim/testsuite/sim/riscv/andi.S | 15 + > sim/testsuite/sim/riscv/auipc.S | 14 + > sim/testsuite/sim/riscv/beq.S | 18 + > sim/testsuite/sim/riscv/beqz.S | 17 + > sim/testsuite/sim/riscv/bge.S | 22 + > sim/testsuite/sim/riscv/bgeu.S | 22 + > sim/testsuite/sim/riscv/bgez.S | 21 + > sim/testsuite/sim/riscv/bgt.S | 20 + > sim/testsuite/sim/riscv/bgtu.S | 20 + > sim/testsuite/sim/riscv/bgtz.S | 19 + > sim/testsuite/sim/riscv/ble.S | 22 + > sim/testsuite/sim/riscv/bleu.S | 22 + > sim/testsuite/sim/riscv/blez.S | 21 + > sim/testsuite/sim/riscv/blt.S | 20 + > sim/testsuite/sim/riscv/bltu.S | 20 + > sim/testsuite/sim/riscv/bltz.S | 19 + > sim/testsuite/sim/riscv/bne.S | 18 + > sim/testsuite/sim/riscv/bnez.S | 17 + > sim/testsuite/sim/riscv/cadd.S | 16 + > sim/testsuite/sim/riscv/caddi.S | 15 + > sim/testsuite/sim/riscv/caddi16sp.S | 15 + > sim/testsuite/sim/riscv/caddi4spn.S | 15 + > sim/testsuite/sim/riscv/call.S | 18 + > sim/testsuite/sim/riscv/cand.S | 16 + > sim/testsuite/sim/riscv/candi.S | 15 + > sim/testsuite/sim/riscv/cor.S | 16 + > sim/testsuite/sim/riscv/csrc.S | 13 + > sim/testsuite/sim/riscv/csrci.S | 12 + > sim/testsuite/sim/riscv/csrrc.S | 13 + > sim/testsuite/sim/riscv/csrrci.S | 12 + > sim/testsuite/sim/riscv/csrrs.S | 13 + > sim/testsuite/sim/riscv/csrrsi.S | 12 + > sim/testsuite/sim/riscv/csrrw.S | 13 + > sim/testsuite/sim/riscv/csrrwi.S | 12 + > sim/testsuite/sim/riscv/csrs.S | 13 + > sim/testsuite/sim/riscv/csrsi.S | 12 + > sim/testsuite/sim/riscv/csrw.S | 13 + > sim/testsuite/sim/riscv/csrwi.S | 12 + > sim/testsuite/sim/riscv/cxor.S | 16 + > sim/testsuite/sim/riscv/div.S | 26 + > sim/testsuite/sim/riscv/divu.S | 16 + > sim/testsuite/sim/riscv/ebreak.S | 11 + > sim/testsuite/sim/riscv/ecall.S | 11 + > sim/testsuite/sim/riscv/fadd-s.S | 20 + > sim/testsuite/sim/riscv/fdiv-s.S | 20 + > sim/testsuite/sim/riscv/fence.S | 11 + > sim/testsuite/sim/riscv/fencei.S | 11 + > sim/testsuite/sim/riscv/flw.S | 22 + > sim/testsuite/sim/riscv/fmadd-s.S | 25 + > sim/testsuite/sim/riscv/fmax-s.S | 31 + > sim/testsuite/sim/riscv/fmin-s.S | 31 + > sim/testsuite/sim/riscv/fmsub-s.S | 25 + > sim/testsuite/sim/riscv/fmul-s.S | 20 + > sim/testsuite/sim/riscv/fsgnj-s.S | 20 + > sim/testsuite/sim/riscv/fsgnjn-s.S | 20 + > sim/testsuite/sim/riscv/fsgnjx-s.S | 20 + > sim/testsuite/sim/riscv/fsub-s.S | 20 + > sim/testsuite/sim/riscv/fsw.S | 22 + > sim/testsuite/sim/riscv/j.S | 14 + > sim/testsuite/sim/riscv/jal.S | 17 + > sim/testsuite/sim/riscv/jalr.S | 20 + > sim/testsuite/sim/riscv/jr.S | 15 + > sim/testsuite/sim/riscv/la.S | 15 + > sim/testsuite/sim/riscv/lb.S | 20 + > sim/testsuite/sim/riscv/lbu.S | 20 + > sim/testsuite/sim/riscv/lh.S | 20 + > sim/testsuite/sim/riscv/lhu.S | 20 + > sim/testsuite/sim/riscv/li.S | 14 + > sim/testsuite/sim/riscv/lla.S | 15 + > sim/testsuite/sim/riscv/lrw.S | 26 + > sim/testsuite/sim/riscv/lui.S | 15 + > sim/testsuite/sim/riscv/lw.S | 20 + > sim/testsuite/sim/riscv/misa-xlen-rv32.S | 19 + > sim/testsuite/sim/riscv/misa-xlen-rv64.S | 19 + > sim/testsuite/sim/riscv/mret.S | 11 + > sim/testsuite/sim/riscv/mul.S | 21 + > sim/testsuite/sim/riscv/mulh-rv32.S | 22 + > sim/testsuite/sim/riscv/mulh-rv64.S | 22 + > sim/testsuite/sim/riscv/mulhsu-rv32.S | 21 + > sim/testsuite/sim/riscv/mulhsu-rv64.S | 21 + > sim/testsuite/sim/riscv/mulhu-rv32.S | 21 + > sim/testsuite/sim/riscv/mulhu-rv64.S | 21 + > sim/testsuite/sim/riscv/mv.S | 15 + > sim/testsuite/sim/riscv/neg.S | 15 + > sim/testsuite/sim/riscv/nop.S | 12 + > sim/testsuite/sim/riscv/not.S | 15 + > sim/testsuite/sim/riscv/or.S | 16 + > sim/testsuite/sim/riscv/ori.S | 15 + > sim/testsuite/sim/riscv/rdcycle.S | 11 + > sim/testsuite/sim/riscv/rdcycleh.S | 11 + > sim/testsuite/sim/riscv/rdinstret.S | 11 + > sim/testsuite/sim/riscv/rdinstreth.S | 11 + > sim/testsuite/sim/riscv/rdtime.S | 11 + > sim/testsuite/sim/riscv/rdtimeh.S | 11 + > sim/testsuite/sim/riscv/rem.S | 26 + > sim/testsuite/sim/riscv/remu.S | 16 + > sim/testsuite/sim/riscv/ret.S | 12 + > sim/testsuite/sim/riscv/sb.S | 21 + > sim/testsuite/sim/riscv/scw.S | 29 + > sim/testsuite/sim/riscv/seqz.S | 18 + > sim/testsuite/sim/riscv/sfence.S | 11 + > sim/testsuite/sim/riscv/sgtz.S | 21 + > sim/testsuite/sim/riscv/sh.S | 21 + > sim/testsuite/sim/riscv/sl.S | 22 + > sim/testsuite/sim/riscv/slt.S | 23 + > sim/testsuite/sim/riscv/slti.S | 22 + > sim/testsuite/sim/riscv/sltiu.S | 23 + > sim/testsuite/sim/riscv/sltu.S | 26 + > sim/testsuite/sim/riscv/sltz.S | 22 + > sim/testsuite/sim/riscv/snez.S | 19 + > sim/testsuite/sim/riscv/sra.S | 21 + > sim/testsuite/sim/riscv/srai.S | 19 + > sim/testsuite/sim/riscv/sret.S | 11 + > sim/testsuite/sim/riscv/srl.S | 21 + > sim/testsuite/sim/riscv/srli.S | 19 + > sim/testsuite/sim/riscv/sub.S | 16 + > sim/testsuite/sim/riscv/sw.S | 21 + > sim/testsuite/sim/riscv/tail.S | 14 + > sim/testsuite/sim/riscv/testutils.inc | 60 + > sim/testsuite/sim/riscv/wfi.S | 11 + > sim/testsuite/sim/riscv/xor.S | 16 + > sim/testsuite/sim/riscv/xori.S | 15 + > 197 files changed, 132967 insertions(+), 10 deletions(-) > create mode 100644 cpu/riscv.cpu > create mode 100644 cpu/riscv.opc > create mode 100644 include/gdb/sim-riscv.h > create mode 100644 opcodes/riscv-cgen-asm.c > create mode 100644 opcodes/riscv-cgen-desc.c > create mode 100644 opcodes/riscv-cgen-desc.h > create mode 100644 opcodes/riscv-cgen-dis.c > create mode 100644 opcodes/riscv-cgen-ibld.c > create mode 100644 opcodes/riscv-cgen-opc.c > create mode 100644 opcodes/riscv-cgen-opc.h > create mode 100644 sim/riscv/Makefile.in > create mode 100644 sim/riscv/aclocal.m4 > create mode 100644 sim/riscv/arch.h > create mode 100644 sim/riscv/arch32.c > create mode 100644 sim/riscv/arch32.h > create mode 100644 sim/riscv/arch64.c > create mode 100644 sim/riscv/arch64.h > create mode 100644 sim/riscv/config.in > create mode 100755 sim/riscv/configure > create mode 100644 sim/riscv/configure.ac > create mode 100644 sim/riscv/cpu32.c > create mode 100644 sim/riscv/cpu32.h > create mode 100644 sim/riscv/cpu64.c > create mode 100644 sim/riscv/cpu64.h > create mode 100644 sim/riscv/cpuall.h > create mode 100644 sim/riscv/cpuall32.h > create mode 100644 sim/riscv/cpuall64.h > create mode 100644 sim/riscv/decode32.c > create mode 100644 sim/riscv/decode32.h > create mode 100644 sim/riscv/decode64.c > create mode 100644 sim/riscv/decode64.h > create mode 100644 sim/riscv/mloop.in > create mode 100644 sim/riscv/model32.c > create mode 100644 sim/riscv/model64.c > create mode 100644 sim/riscv/riscv-sim.h > create mode 100644 sim/riscv/riscv.c > create mode 100644 sim/riscv/sem32.c > create mode 100644 sim/riscv/sem64.c > create mode 100644 sim/riscv/sim-if.c > create mode 100644 sim/riscv/sim-main.h > create mode 100644 sim/riscv/traps.c > create mode 100644 sim/testsuite/sim/riscv/ChangeLog > create mode 100644 sim/testsuite/sim/riscv/add.S > create mode 100644 sim/testsuite/sim/riscv/addi.S > create mode 100644 sim/testsuite/sim/riscv/alltests.exp > create mode 100644 sim/testsuite/sim/riscv/amoaddw.S > create mode 100644 sim/testsuite/sim/riscv/amoandw.S > create mode 100644 sim/testsuite/sim/riscv/amomaxuw.S > create mode 100644 sim/testsuite/sim/riscv/amomaxw.S > create mode 100644 sim/testsuite/sim/riscv/amominuw.S > create mode 100644 sim/testsuite/sim/riscv/amominw.S > create mode 100644 sim/testsuite/sim/riscv/amoorw.S > create mode 100644 sim/testsuite/sim/riscv/amoswapw.S > create mode 100644 sim/testsuite/sim/riscv/amoxorw.S > create mode 100644 sim/testsuite/sim/riscv/and.S > create mode 100644 sim/testsuite/sim/riscv/andi.S > create mode 100644 sim/testsuite/sim/riscv/auipc.S > create mode 100644 sim/testsuite/sim/riscv/beq.S > create mode 100644 sim/testsuite/sim/riscv/beqz.S > create mode 100644 sim/testsuite/sim/riscv/bge.S > create mode 100644 sim/testsuite/sim/riscv/bgeu.S > create mode 100644 sim/testsuite/sim/riscv/bgez.S > create mode 100644 sim/testsuite/sim/riscv/bgt.S > create mode 100644 sim/testsuite/sim/riscv/bgtu.S > create mode 100644 sim/testsuite/sim/riscv/bgtz.S > create mode 100644 sim/testsuite/sim/riscv/ble.S > create mode 100644 sim/testsuite/sim/riscv/bleu.S > create mode 100644 sim/testsuite/sim/riscv/blez.S > create mode 100644 sim/testsuite/sim/riscv/blt.S > create mode 100644 sim/testsuite/sim/riscv/bltu.S > create mode 100644 sim/testsuite/sim/riscv/bltz.S > create mode 100644 sim/testsuite/sim/riscv/bne.S > create mode 100644 sim/testsuite/sim/riscv/bnez.S > create mode 100644 sim/testsuite/sim/riscv/cadd.S > create mode 100644 sim/testsuite/sim/riscv/caddi.S > create mode 100644 sim/testsuite/sim/riscv/caddi16sp.S > create mode 100644 sim/testsuite/sim/riscv/caddi4spn.S > create mode 100644 sim/testsuite/sim/riscv/call.S > create mode 100644 sim/testsuite/sim/riscv/cand.S > create mode 100644 sim/testsuite/sim/riscv/candi.S > create mode 100644 sim/testsuite/sim/riscv/cor.S > create mode 100644 sim/testsuite/sim/riscv/csrc.S > create mode 100644 sim/testsuite/sim/riscv/csrci.S > create mode 100644 sim/testsuite/sim/riscv/csrrc.S > create mode 100644 sim/testsuite/sim/riscv/csrrci.S > create mode 100644 sim/testsuite/sim/riscv/csrrs.S > create mode 100644 sim/testsuite/sim/riscv/csrrsi.S > create mode 100644 sim/testsuite/sim/riscv/csrrw.S > create mode 100644 sim/testsuite/sim/riscv/csrrwi.S > create mode 100644 sim/testsuite/sim/riscv/csrs.S > create mode 100644 sim/testsuite/sim/riscv/csrsi.S > create mode 100644 sim/testsuite/sim/riscv/csrw.S > create mode 100644 sim/testsuite/sim/riscv/csrwi.S > create mode 100644 sim/testsuite/sim/riscv/cxor.S > create mode 100644 sim/testsuite/sim/riscv/div.S > create mode 100644 sim/testsuite/sim/riscv/divu.S > create mode 100644 sim/testsuite/sim/riscv/ebreak.S > create mode 100644 sim/testsuite/sim/riscv/ecall.S > create mode 100644 sim/testsuite/sim/riscv/fadd-s.S > create mode 100644 sim/testsuite/sim/riscv/fdiv-s.S > create mode 100644 sim/testsuite/sim/riscv/fence.S > create mode 100644 sim/testsuite/sim/riscv/fencei.S > create mode 100644 sim/testsuite/sim/riscv/flw.S > create mode 100644 sim/testsuite/sim/riscv/fmadd-s.S > create mode 100644 sim/testsuite/sim/riscv/fmax-s.S > create mode 100644 sim/testsuite/sim/riscv/fmin-s.S > create mode 100644 sim/testsuite/sim/riscv/fmsub-s.S > create mode 100644 sim/testsuite/sim/riscv/fmul-s.S > create mode 100644 sim/testsuite/sim/riscv/fsgnj-s.S > create mode 100644 sim/testsuite/sim/riscv/fsgnjn-s.S > create mode 100644 sim/testsuite/sim/riscv/fsgnjx-s.S > create mode 100644 sim/testsuite/sim/riscv/fsub-s.S > create mode 100644 sim/testsuite/sim/riscv/fsw.S > create mode 100644 sim/testsuite/sim/riscv/j.S > create mode 100644 sim/testsuite/sim/riscv/jal.S > create mode 100644 sim/testsuite/sim/riscv/jalr.S > create mode 100644 sim/testsuite/sim/riscv/jr.S > create mode 100644 sim/testsuite/sim/riscv/la.S > create mode 100644 sim/testsuite/sim/riscv/lb.S > create mode 100644 sim/testsuite/sim/riscv/lbu.S > create mode 100644 sim/testsuite/sim/riscv/lh.S > create mode 100644 sim/testsuite/sim/riscv/lhu.S > create mode 100644 sim/testsuite/sim/riscv/li.S > create mode 100644 sim/testsuite/sim/riscv/lla.S > create mode 100644 sim/testsuite/sim/riscv/lrw.S > create mode 100644 sim/testsuite/sim/riscv/lui.S > create mode 100644 sim/testsuite/sim/riscv/lw.S > create mode 100644 sim/testsuite/sim/riscv/misa-xlen-rv32.S > create mode 100644 sim/testsuite/sim/riscv/misa-xlen-rv64.S > create mode 100644 sim/testsuite/sim/riscv/mret.S > create mode 100644 sim/testsuite/sim/riscv/mul.S > create mode 100644 sim/testsuite/sim/riscv/mulh-rv32.S > create mode 100644 sim/testsuite/sim/riscv/mulh-rv64.S > create mode 100644 sim/testsuite/sim/riscv/mulhsu-rv32.S > create mode 100644 sim/testsuite/sim/riscv/mulhsu-rv64.S > create mode 100644 sim/testsuite/sim/riscv/mulhu-rv32.S > create mode 100644 sim/testsuite/sim/riscv/mulhu-rv64.S > create mode 100644 sim/testsuite/sim/riscv/mv.S > create mode 100644 sim/testsuite/sim/riscv/neg.S > create mode 100644 sim/testsuite/sim/riscv/nop.S > create mode 100644 sim/testsuite/sim/riscv/not.S > create mode 100644 sim/testsuite/sim/riscv/or.S > create mode 100644 sim/testsuite/sim/riscv/ori.S > create mode 100644 sim/testsuite/sim/riscv/rdcycle.S > create mode 100644 sim/testsuite/sim/riscv/rdcycleh.S > create mode 100644 sim/testsuite/sim/riscv/rdinstret.S > create mode 100644 sim/testsuite/sim/riscv/rdinstreth.S > create mode 100644 sim/testsuite/sim/riscv/rdtime.S > create mode 100644 sim/testsuite/sim/riscv/rdtimeh.S > create mode 100644 sim/testsuite/sim/riscv/rem.S > create mode 100644 sim/testsuite/sim/riscv/remu.S > create mode 100644 sim/testsuite/sim/riscv/ret.S > create mode 100644 sim/testsuite/sim/riscv/sb.S > create mode 100644 sim/testsuite/sim/riscv/scw.S > create mode 100644 sim/testsuite/sim/riscv/seqz.S > create mode 100644 sim/testsuite/sim/riscv/sfence.S > create mode 100644 sim/testsuite/sim/riscv/sgtz.S > create mode 100644 sim/testsuite/sim/riscv/sh.S > create mode 100644 sim/testsuite/sim/riscv/sl.S > create mode 100644 sim/testsuite/sim/riscv/slt.S > create mode 100644 sim/testsuite/sim/riscv/slti.S > create mode 100644 sim/testsuite/sim/riscv/sltiu.S > create mode 100644 sim/testsuite/sim/riscv/sltu.S > create mode 100644 sim/testsuite/sim/riscv/sltz.S > create mode 100644 sim/testsuite/sim/riscv/snez.S > create mode 100644 sim/testsuite/sim/riscv/sra.S > create mode 100644 sim/testsuite/sim/riscv/srai.S > create mode 100644 sim/testsuite/sim/riscv/sret.S > create mode 100644 sim/testsuite/sim/riscv/srl.S > create mode 100644 sim/testsuite/sim/riscv/srli.S > create mode 100644 sim/testsuite/sim/riscv/sub.S > create mode 100644 sim/testsuite/sim/riscv/sw.S > create mode 100644 sim/testsuite/sim/riscv/tail.S > create mode 100644 sim/testsuite/sim/riscv/testutils.inc > create mode 100644 sim/testsuite/sim/riscv/wfi.S > create mode 100644 sim/testsuite/sim/riscv/xor.S > create mode 100644 sim/testsuite/sim/riscv/xori.S > > -- > 2.9.5 >
Attachment:
0002-RISC-V-Add-cgen-based-simulator-port.patch.gz
Description: application/gzip
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