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Re: Linker support for Harvard Architecture
- From: "Ian Lance Taylor via binutils" <binutils at sourceware dot org>
- To: Haim Shimonovich <Haim dot Shimonovich at ceva-dsp dot com>
- Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Wed, 31 Jul 2019 05:55:10 -0700
- Subject: Re: Linker support for Harvard Architecture
- References: <firstname.lastname@example.org>
- Reply-to: Ian Lance Taylor <iant at google dot com>
On Wed, Jul 31, 2019 at 4:59 AM Haim Shimonovich
> I am trying to support a processor that contains 2 address spaces(one for code and one for data).
> The current implementation of the Linker prevents me from mapping a code section and a data section to the same address.
> I get the following error:
> section .data.internal LMA [0000000000000000,0000000000002343] overlaps section .text LMA [0000000000000000,00000000000002ff]
> Is there a known way to support this kind of memory configuration(without using overlays)?
What I have done in the past is simply put the data section at a very
large address, larger than the addressable space of the text section.
Then fix up the data addresses in the loader.