This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH v2 1/5] RISC-V: Fix doc for .insn
- From: Kito Cheng <kito dot cheng at sifive dot com>
- To: binutils at sourceware dot org, jimw at sifive dot com
- Cc: Kito Cheng <kito dot cheng at sifive dot com>
- Date: Tue, 2 Jul 2019 17:57:57 +0800
- Subject: [PATCH v2 1/5] RISC-V: Fix doc for .insn
gas/ChangeLog:
* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
type and fix typo.
---
gas/doc/c-riscv.texi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 42d1ce3e5f..5c30db1b83 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -286,7 +286,7 @@ Opcode space for msub instruction.
@item AMO
Opcode space for atomic memory operation instructions.
-@item MISC_IMM
+@item MISC_MEM
Opcode space for misc instructions.
@item SYSTEM
@@ -344,10 +344,10 @@ with the @samp{.insn} pseudo directive:
@item SB type: .insn sb opcode, func3, rd, rs1, symbol
@itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
@verbatim
-+--------------+-----+-----+-------+-------------+-------------+
-| simm21[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
-+--------------+-----+-----+-------+-------------+-------------+
-31 25 20 15 12 7 0
++------------+--------------+-----+-----+-------+-------------+-------------+--------+
+| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
++------------+--------------+-----+-----+-------+-------------+-------------+--------+
+31 30 25 20 15 12 7 0
@end verbatim
@item U type: .insn u opcode, rd, simm20
--
2.17.1