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Re: [PATCH] x86: add missing pseudo ops for VPCLMULQDQ ISA extension
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Thu, 27 Jun 2019 10:00:21 -0700
- Subject: Re: [PATCH] x86: add missing pseudo ops for VPCLMULQDQ ISA extension
- References: <5D12379E020000780023B04F@prv1-mh.provo.novell.com>
On Tue, Jun 25, 2019 at 8:03 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> While the ISA extensions doc suggests them to be made available just
> like the SDM does for the PCLMULQDQ ISA extension, these weren't added
> when supposrt for the new extension was introduced.
>
> Also make sure the 64-bit non-AVX512 test actually tests VEX encodings,
> not EVEX ones.
>
> gas/
> 2019-06-25 Jan Beulich <jbeulich@suse.com>
>
> * testsuite/gas/i386/avx512f_vpclmulqdq.s,
> testsuite/gas/i386/avx512vl_vpclmulqdq.s,
> testsuite/gas/i386/vpclmulqdq.s,
> testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s,
> testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Add pseudo ops.
> * testsuite/gas/i386/x86-64-vpclmulqdq.s: Likewise. Don't use
> high 16 [xy]mm registers.
>
> * testsuite/gas/i386/avx512f_vpclmulqdq.d,
> testsuite/gas/i386/avx512f_vpclmulqdq-intel.d,
> testsuite/gas/i386/avx512vl_vpclmulqdq.d,
> testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d,
> testsuite/gas/i386/vpclmulqdq.d,
> testsuite/gas/i386/vpclmulqdq-intel.d,
> testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d,
> testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d,
> testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d,
> testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d,
> testsuite/gas/i386/x86-64-vpclmulqdq.d,
> testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Adjust
> expectations.
>
> opcodes/
> 2019-06-25 Jan Beulich <jbeulich@suse.com>
>
> * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
> * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
> vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
> * i386-tbl.h: Re-generate.
>
OK.
Thanks.
--
H.J.