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Re: [PATCH 3/3] RISC-V: Add r4 format for r type with 4 register operands

From: Jim Wilson <jimw at sifive dot com>
To: Kito Cheng <kito at andestech dot com>
Cc: Binutils <binutils at sourceware dot org>, Kito Cheng <kito dot cheng at gmail dot com>
Date: Tue, 28 May 2019 23:49:00 -0700
Subject: Re: [PATCH 3/3] RISC-V: Add r4 format for r type with 4 register operands
References: <1558939175-51429-1-git-send-email-kito@andestech.com> <1558939175-51429-3-git-send-email-kito@andestech.com>

On Sun, May 26, 2019 at 11:37 PM Kito Cheng <kito@andestech.com> wrote:
> gas/ChangeLog:
>         * doc/c-riscv.texi (Instruction Formats): Add r4 type.
> opcodes/ChangeLog:
>         * riscv-opc.c (riscv_insn_types): Add r4 type.

There should be testcases added for the new r4 type.  Otherwise this looks OK.

Jim

References:
- [PATCH 1/3] RISC-V: Fix doc for .insn
  - From: Kito Cheng
- [PATCH 3/3] RISC-V: Add r4 format for r type with 4 register operands
  - From: Kito Cheng

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