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[PATCH 2/3] RISC-V: sb/uj format named b/j in latest spec
- From: Kito Cheng <kito at andestech dot com>
- To: <jimw at sifive dot com>, Binutils <binutils at sourceware dot org>, <kito dot cheng at gmail dot com>
- Date: Mon, 27 May 2019 14:39:34 +0800
- Subject: [PATCH 2/3] RISC-V: sb/uj format named b/j in latest spec
- References: <1558939175-51429-1-git-send-email-kito@andestech.com>
From: Kito Cheng <kito.cheng@gmail.com>
- We also keep sb and uj for backward compatibility.
gas/ChangeLog:
* doc/c-riscv.texi (Instruction Formats): Add b and j type.
opcode/ChangeLog:
* riscv-opc.c (riscv_insn_types): Add b and j type.
---
gas/doc/c-riscv.texi | 3 +++
opcodes/riscv-opc.c | 11 +++++++++++
2 files changed, 14 insertions(+)
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 5c30db1..a280ea2 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -343,6 +343,8 @@ with the @samp{.insn} pseudo directive:
@item SB type: .insn sb opcode, func3, rd, rs1, symbol
@itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
+@itemx B type: .insn s opcode, func3, rd, rs1, symbol
+@itemx B type: .insn s opcode, func3, rd, simm12(rs1)
@verbatim
+------------+--------------+-----+-----+-------+-------------+-------------+--------+
| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
@@ -359,6 +361,7 @@ with the @samp{.insn} pseudo directive:
@end verbatim
@item UJ type: .insn uj opcode, rd, symbol
+@itemx J type: .insn j opcode, rd, symbol
@verbatim
+------------+--------------+------------+---------------+----+-------------+
| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bd65259..03f0cd1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -831,12 +831,23 @@ const struct riscv_opcode riscv_insn_types[] =
{"sb", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
+
+{"b", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
+
{"u", 0, {"I", 0}, "O4,d,u", 0, 0, match_opcode, 0 },
{"u", 0, {"I", 0}, "O4,D,u", 0, 0, match_opcode, 0 },
{"uj", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
{"uj", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+
{"cr", 0, {"C", 0}, "O2,CF4,d,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,D,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,d,CT", 0, 0, match_opcode, 0 },
--
1.8.3.1