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[Patch, Arm, Gas] PR24559: Fix pseudo load-operations for Armv8-M Baseline
- From: "Andre Vieira (lists)" <andre dot simoesdiasvieira at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Nick Clifton <nickc at redhat dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- Date: Thu, 16 May 2019 17:24:50 +0100
- Subject: [Patch, Arm, Gas] PR24559: Fix pseudo load-operations for Armv8-M Baseline
Hi,
This patch fixes PR24559 by making sure the size restriction for Thumb-1
targets is relaxed for Armv8-M Baseline to allow for replacing pseudo
load-operations with the 32-bit Thumb MOVW instruction if the immediate
fits its range.
Is this OK for trunk?
Tested on arm-none-eabi, arm-pe and arm-vxworks.
Cheers,
Andre
gas/ChangeLog
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR24559
* config/tc-arm.c (move_or_literal_pool): Set size_req to 0
for MOVW replacement.
* testsuite/gas/arm/load-pseudo.s: New test input.
* testsuite/gas/arm/m0-load-pseudo.d: New test.
* testsuite/gas/arm/m23-load-pseudo.d: New test.
* testsuite/gas/arm/m33-load-pseudo.d: New test.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 793ac58de29f149f937658d7244be6786aef96b7..9d4b4eaec4c79a82d48b8ff09032c87f1bcf3c82 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -8699,6 +8699,11 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
inst.instruction |= (imm & 0x0800) << 15;
inst.instruction |= (imm & 0x0700) << 4;
inst.instruction |= (imm & 0x00ff);
+ /* In case this replacement is being done on Armv8-M
+ Baseline we need to make sure to disable the
+ instruction size check, as otherwise GAS will reject
+ the use of this T32 instruction. */
+ inst.size_req = 0;
return TRUE;
}
}
diff --git a/gas/testsuite/gas/arm/load-pseudo.s b/gas/testsuite/gas/arm/load-pseudo.s
new file mode 100644
index 0000000000000000000000000000000000000000..2102522b718d940e666a24399818bf89281f34dc
--- /dev/null
+++ b/gas/testsuite/gas/arm/load-pseudo.s
@@ -0,0 +1,3 @@
+.syntax unified
+ldr r0, =(0x30)
+ldr r0, =(0x70000000)
diff --git a/gas/testsuite/gas/arm/m0-load-pseudo.d b/gas/testsuite/gas/arm/m0-load-pseudo.d
new file mode 100644
index 0000000000000000000000000000000000000000..cc7e08518ff0889d0a46ce20572c341759f8795f
--- /dev/null
+++ b/gas/testsuite/gas/arm/m0-load-pseudo.d
@@ -0,0 +1,12 @@
+# name: Load pseudo-operation for Cortex-M0
+# as: -mcpu=cortex-m0
+# objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
+# source: load-pseudo.s
+
+.*: +file format .*arm.*
+
+
+Disassembly of section .text:
+[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000004 [^>]*>\)
+[^>]*> 4801 ldr r0, \[pc, #4\] ; \(00000008 [^>]*>\)
+#...
diff --git a/gas/testsuite/gas/arm/m23-load-pseudo.d b/gas/testsuite/gas/arm/m23-load-pseudo.d
new file mode 100644
index 0000000000000000000000000000000000000000..2e0dbe5479b398a609da2fd153a25db2a7f88be2
--- /dev/null
+++ b/gas/testsuite/gas/arm/m23-load-pseudo.d
@@ -0,0 +1,12 @@
+# name: Load pseudo-operation for Cortex-M23
+# as: -mcpu=cortex-m23
+# objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
+# source: load-pseudo.s
+
+.*: +file format .*arm.*
+
+
+Disassembly of section .text:
+[^>]*> f240 0030 movw r0, #48 ; 0x30
+[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000008 [^>]*>\)
+#...
diff --git a/gas/testsuite/gas/arm/m33-load-pseudo.d b/gas/testsuite/gas/arm/m33-load-pseudo.d
new file mode 100644
index 0000000000000000000000000000000000000000..e77bffd0f4d9f1aa2c11e232f95ca422e7927391
--- /dev/null
+++ b/gas/testsuite/gas/arm/m33-load-pseudo.d
@@ -0,0 +1,11 @@
+# name: Load pseudo-operation for Cortex-M33
+# as: -mcpu=cortex-m33
+# objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
+# source: load-pseudo.s
+
+.*: +file format .*arm.*
+
+
+Disassembly of section .text:
+[^>]*> f04f 0030 mov.w r0, #48 ; 0x30
+[^>]*> f04f 40e0 mov.w r0, #1879048192 ; 0x70000000