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[PATCH 11/16] [binutils][aarch64] New sve_shift_tsz_bhsd iclass.
- From: Matthew Malcomson <Matthew dot Malcomson at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: nd <nd at arm dot com>, Matthew Malcomson <Matthew dot Malcomson at arm dot com>
- Date: Wed, 1 May 2019 14:44:39 +0000
- Subject: [PATCH 11/16] [binutils][aarch64] New sve_shift_tsz_bhsd iclass.
- References: <1556721866-21052-1-git-send-email-matthew.malcomson@arm.com>
This new iclass encodes the variant by which is the most significant bit
used of bits 23-22:20-19, where those bits are usually part of a
given constant operand.
include/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
iclass.
opcodes/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass decode.
---
include/opcode/aarch64.h | 1 +
opcodes/aarch64-asm.c | 1 +
opcodes/aarch64-dis.c | 11 +++++++++++
3 files changed, 13 insertions(+)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index ce9955d..285af27 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -595,6 +595,7 @@ enum aarch64_insn_class
sve_size_sd2,
sve_size_013,
sve_shift_tsz_hsd,
+ sve_shift_tsz_bhsd,
testbranch,
cryptosm3,
cryptosm4,
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 6be17f9..ad50598 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1626,6 +1626,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
case sve_shift_pred:
case sve_shift_unpred:
case sve_shift_tsz_hsd:
+ case sve_shift_tsz_bhsd:
/* For indices and shift amounts, the variant is encoded as
part of the immediate. */
break;
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 5571ab6..b42e4d5 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2832,6 +2832,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = i;
break;
+ case sve_shift_tsz_bhsd:
+ i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
+ if (i == 0)
+ return FALSE;
+ while (i != 1)
+ {
+ i >>= 1;
+ variant += 1;
+ }
+ break;
+
case sve_shift_tsz_hsd:
i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
if (i == 0)
--
2.7.4