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Re: [PATCH] [MIPS] Add RDHWR with the SEL field for MIPSR6
Hi Paul,
I am not approved for writes, yet.
Faraz
________________________________
From: Paul Hua <paul.hua.gm@gmail.com>
Sent: Monday, April 8, 2019 8:09:54 PM
To: Faraz Shahbazker
Cc: binutils@sourceware.org
Subject: Re: [PATCH] [MIPS] Add RDHWR with the SEL field for MIPSR6
Ok, please apply.
On Tue, Apr 9, 2019 at 9:23 AM Faraz Shahbazker
<fshahbazker@wavecomp.com> wrote:
>
> From: Robert Suchanek <robert.suchanek@mips.com>
>
> In Release 6 of the MIPS architecture [1], instruction RDHWR supports
> a 3rd operand to serve as the 3-bit select field for the hardware
> register.
>
> [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
> Instruction Set Manual", Imagination Technologies Ltd., Document
> Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
> "Alphabetical List of Instructions", pp. 332-334
>
> opcodes/
> * mips-opc.c (mips_builtin_opcodes): Add new RDHWR format.
>
> gas/
> * testsuite/gas/mips/mips.exp: Add new tests.
> * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
> the SEL field.
> * testsuite/gas/mips/mipsr6@hwr-names.d: New file.
> ---
> gas/testsuite/gas/mips/hwr-names.s | 11 +++++++
> gas/testsuite/gas/mips/mips.exp | 2 ++
> gas/testsuite/gas/mips/mipsr6@hwr-names.d | 51 +++++++++++++++++++++++++++++++
> opcodes/mips-opc.c | 1 +
> 4 files changed, 65 insertions(+)
> create mode 100644 gas/testsuite/gas/mips/mipsr6@hwr-names.d
>
> diff --git a/gas/testsuite/gas/mips/hwr-names.s b/gas/testsuite/gas/mips/hwr-names.s
> index f0e056b..41e7b49 100644
> --- a/gas/testsuite/gas/mips/hwr-names.s
> +++ b/gas/testsuite/gas/mips/hwr-names.s
> @@ -40,5 +40,16 @@ text_label:
> rdhwr $0, $30
> rdhwr $0, $31
>
> + .ifdef r6
> + rdhwr $0, $4, 0
> + rdhwr $0, $4, 1
> + rdhwr $0, $4, 2
> + rdhwr $0, $4, 3
> + rdhwr $0, $4, 4
> + rdhwr $0, $4, 5
> + rdhwr $0, $4, 6
> + rdhwr $0, $4, 7
> + .endif
> +
> # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
> .space 8
> diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
> index 31e155b..a009c6e 100644
> --- a/gas/testsuite/gas/mips/mips.exp
> +++ b/gas/testsuite/gas/mips/mips.exp
> @@ -1342,6 +1342,8 @@ if { [istarget mips*-*-vxworks*] } {
> run_dump_test "hwr-names-numeric"
> run_dump_test "hwr-names-mips32r2"
> run_dump_test "hwr-names-mips64r2"
> + run_dump_test_arches "hwr-names" [mips_arch_list_matching mips32r6 \
> + !micromipsr6]
>
> run_dump_test "ldstla-32"
> run_dump_test "ldstla-32-mips3"
> diff --git a/gas/testsuite/gas/mips/mipsr6@hwr-names.d b/gas/testsuite/gas/mips/mipsr6@hwr-names.d
> new file mode 100644
> index 0000000..e44a120
> --- /dev/null
> +++ b/gas/testsuite/gas/mips/mipsr6@hwr-names.d
> @@ -0,0 +1,51 @@
> +#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32r6 -M gpr-names=numeric,hwr-names=mips32r6
> +#name: MIPS HWR disassembly (mips32r6)
> +#as: -32
> +#source: hwr-names.s
> +
> +# Check objdump's handling of -M hwr-names=foo options.
> +
> +.*: +file format .*mips.*
> +
> +Disassembly of section .text:
> +0+0000 <[^>]*> 7c00003b rdhwr \$0,hwr_cpunum
> +0+0004 <[^>]*> 7c00083b rdhwr \$0,hwr_synci_step
> +0+0008 <[^>]*> 7c00103b rdhwr \$0,hwr_cc
> +0+000c <[^>]*> 7c00183b rdhwr \$0,hwr_ccres
> +0+0010 <[^>]*> 7c00203b rdhwr \$0,\$4
> +0+0014 <[^>]*> 7c00283b rdhwr \$0,\$5
> +0+0018 <[^>]*> 7c00303b rdhwr \$0,\$6
> +0+001c <[^>]*> 7c00383b rdhwr \$0,\$7
> +0+0020 <[^>]*> 7c00403b rdhwr \$0,\$8
> +0+0024 <[^>]*> 7c00483b rdhwr \$0,\$9
> +0+0028 <[^>]*> 7c00503b rdhwr \$0,\$10
> +0+002c <[^>]*> 7c00583b rdhwr \$0,\$11
> +0+0030 <[^>]*> 7c00603b rdhwr \$0,\$12
> +0+0034 <[^>]*> 7c00683b rdhwr \$0,\$13
> +0+0038 <[^>]*> 7c00703b rdhwr \$0,\$14
> +0+003c <[^>]*> 7c00783b rdhwr \$0,\$15
> +0+0040 <[^>]*> 7c00803b rdhwr \$0,\$16
> +0+0044 <[^>]*> 7c00883b rdhwr \$0,\$17
> +0+0048 <[^>]*> 7c00903b rdhwr \$0,\$18
> +0+004c <[^>]*> 7c00983b rdhwr \$0,\$19
> +0+0050 <[^>]*> 7c00a03b rdhwr \$0,\$20
> +0+0054 <[^>]*> 7c00a83b rdhwr \$0,\$21
> +0+0058 <[^>]*> 7c00b03b rdhwr \$0,\$22
> +0+005c <[^>]*> 7c00b83b rdhwr \$0,\$23
> +0+0060 <[^>]*> 7c00c03b rdhwr \$0,\$24
> +0+0064 <[^>]*> 7c00c83b rdhwr \$0,\$25
> +0+0068 <[^>]*> 7c00d03b rdhwr \$0,\$26
> +0+006c <[^>]*> 7c00d83b rdhwr \$0,\$27
> +0+0070 <[^>]*> 7c00e03b rdhwr \$0,\$28
> +0+0074 <[^>]*> 7c00e83b rdhwr \$0,\$29
> +0+0078 <[^>]*> 7c00f03b rdhwr \$0,\$30
> +0+007c <[^>]*> 7c00f83b rdhwr \$0,\$31
> +0+0080 <[^>]*> 7c00203b rdhwr \$0,\$4
> +0+0084 <[^>]*> 7c00207b rdhwr \$0,\$4,1
> +0+0088 <[^>]*> 7c0020bb rdhwr \$0,\$4,2
> +0+008c <[^>]*> 7c0020fb rdhwr \$0,\$4,3
> +0+0090 <[^>]*> 7c00213b rdhwr \$0,\$4,4
> +0+0094 <[^>]*> 7c00217b rdhwr \$0,\$4,5
> +0+0098 <[^>]*> 7c0021bb rdhwr \$0,\$4,6
> +0+009c <[^>]*> 7c0021fb rdhwr \$0,\$4,7
> + \.\.\.
> diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
> index 837da6b..91f6027 100644
> --- a/opcodes/mips-opc.c
> +++ b/opcodes/mips-opc.c
> @@ -1781,6 +1781,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
> {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 },
> {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 },
> {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 },
> +{"rdhwr", "t,K,+O", 0x7c00003b, 0xffe0063f, WR_1, 0, I37, 0, 0 },
> {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 },
> /* rfe is moved below as it now conflicts with tlbgp */
> {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 },
> --
> 2.9.5
>